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[PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0
From: |
Peter Maydell |
Subject: |
[PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0 |
Date: |
Tue, 19 Nov 2019 13:31:44 +0000 |
From: Richard Henderson <address@hidden>
Armv8-A removes UNPREDICTABLE for R13 for these cases.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
since these cases are still UNPREDICTABLE for v8M]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b285b23858e..4d5d4bd8886 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8927,15 +8927,17 @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a)
static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
{
TCGv_i32 addr;
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rd == 15 || a->rn == 15 || a->rt == 15
|| a->rd == a->rn || a->rd == a->rt
- || (s->thumb && (a->rd == 13 || a->rt == 13))
+ || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
|| (mop == MO_64
&& (a->rt2 == 15
|| a->rd == a->rt2
- || (s->thumb && a->rt2 == 13)))) {
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;
}
@@ -9084,13 +9086,15 @@ static bool trans_STLH(DisasContext *s, arg_STL *a)
static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
{
TCGv_i32 addr;
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
/* We UNDEF for these UNPREDICTABLE cases. */
if (a->rn == 15 || a->rt == 15
- || (s->thumb && a->rt == 13)
+ || (!v8a && s->thumb && a->rt == 13)
|| (mop == MO_64
&& (a->rt2 == 15 || a->rt == a->rt2
- || (s->thumb && a->rt2 == 13)))) {
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;
}
--
2.20.1
- [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19
- [PULL 1/7] pl031: Expose RTCICR as proper WC register, Peter Maydell, 2019/11/19
- [PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status, Peter Maydell, 2019/11/19
- [PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes, Peter Maydell, 2019/11/19
- [PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller, Peter Maydell, 2019/11/19
- [PULL 5/7] target/arm: Do not reject rt == rt2 for strexd, Peter Maydell, 2019/11/19
- [PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0,
Peter Maydell <=
- [PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY, Peter Maydell, 2019/11/19
- Re: [PULL 0/7] target-arm queue, Peter Maydell, 2019/11/19