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Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar re
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers |
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Date: |
Sat, 5 Dec 2020 06:44:06 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/4/20 4:40 PM, Philippe Mathieu-Daudé wrote:
> Back to the patch, instead of aliasing FPU registers to the MSA ones
> (even when MSA is absent), we now alias the MSA ones to the FPU ones
> (only when MSA is present). This is what I call the "inverted logic".
>
> BTW the point of this change is simply to be able to extract the MSA
> code out of the huge translate.c.
Yes, I see that at the end of the series. Have a
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
[PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/02
[PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/02