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Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() hel
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper |
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Date: |
Wed, 16 Dec 2020 11:55:20 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 |
On 12/16/20 12:48 AM, Philippe Mathieu-Daudé wrote:
> On 12/16/20 12:27 AM, Richard Henderson wrote:
>> On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
>>> +bool isa_rel6_available(const CPUMIPSState *env)
>>> +{
>>> + if (TARGET_LONG_BITS == 64) {
>>> + return cpu_supports_isa(env, ISA_MIPS64R6);
>>> + }
>>> + return cpu_supports_isa(env, ISA_MIPS32R6);
>>> +}
>>
>> So... does qemu-system-mips64 support 32-bit cpus?
>
> Well... TBH I never tested it :S It looks the TCG code
> is compiled with 64-bit TL registers, the machine address
> space is 64-bit regardless the CPU, and I see various
> #ifdef MIPS64 code that look dubious with 32-bit CPU.
I don't think 32-bit CPUs on 64-bit build currently work
well, see:
382 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
383 # ifdef TARGET_MIPS64
384 /* Enable 64-bit register mode. */
385 env->CP0_Status |= (1 << CP0St_PX);
386 # endif
387 # ifdef TARGET_ABI_MIPSN64
388 /* Enable 64-bit address mode. */
389 env->CP0_Status |= (1 << CP0St_UX);
390 # endif
391 /*
392 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
393 * hardware registers.
394 */
395 env->CP0_HWREna |= 0x0000000F;
396 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
397 env->CP0_Status |= (1 << CP0St_CU1);
398 }
399 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) {
400 env->CP0_Status |= (1 << CP0St_MX);
401 }
402 # if defined(TARGET_MIPS64)
403 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is
writable. */
404 if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
405 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
406 env->CP0_Status |= (1 << CP0St_FR);
407 }
408 # endif
Or:
1018 void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1019 {
1020 #if defined(TARGET_MIPS64)
1021 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1022 #else
1023 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1024 #endif
1025 }
1038 void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1039 {
1040 #if defined(TARGET_MIPS64)
1041 /* PWEn = 0. Hardware page table walking is not implemented. */
1042 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 &
0x5C00003F);
1043 #else
1044 env->CP0_PWCtl = (arg1 & 0x800000FF);
1045 #endif
1046 }
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, (continued)
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Richard Henderson, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper,
Philippe Mathieu-Daudé <=
[PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 07/24] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15