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Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() hel
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper |
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Date: |
Wed, 16 Dec 2020 11:59:08 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 |
On 12/16/20 11:50 AM, Philippe Mathieu-Daudé wrote:
> On 12/16/20 4:14 AM, Jiaxun Yang wrote:
>> 在 2020/12/16 上午10:50, Jiaxun Yang 写道:
>>>
>>>
>>> TBH I do think it doesn't sounds like a good idea to make 32-bit
>>> and 64-bit different. In fact ISA_MIPS32R6 is always set for targets
>>> with ISA_MIPS64R6.
>>>
>>> We're treating MIPS64R6 as a superset of MIPS32R6, and ISA_MIPS3
>>> is used to tell if a CPU supports 64-bit.
I suppose you are talking about the CPU definitions
(CPU_MIPS32R6/CPU_MIPS64R6).
>
> Which is why I don't understand why they are 2 ISA_MIPS32R6/ISA_MIPS64R6
> definitions.
My comment is about the ISA definitions:
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS64R5 0x0000000000001000ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_MIPS64R6 0x0000000000004000ULL
>
>>>
>>> FYI:
>>> https://commons.wikimedia.org/wiki/File:MIPS_instruction_set_family.svg
>>
>> Just add more cents here...
>> The current method we handle R6 makes me a little bit annoying.
>>
>> Given that MIPS is backward compatible until R5, and R6 reorganized a lot
>> of opcodes, I do think decoding procdure of R6 should be dedicated from
>> the rest,
>> otherwise we may fall into the hell of finding difference between R6 and
>> previous
>> ISAs, also I've heard some R6 only ASEs is occupying opcodes marked as
>> "removed in R6", so it doesn't looks like a wise idea to check removed
>> in R6
>> in helpers.
>
> I'm not sure I understood well your comment, but I also find how
> R6 is handled messy...
>
> I'm doing this removal (from helper to decoder) with the decodetree
> conversion.
>
>> So we may end up having four series of decodetrees for ISA
>> Series1: MIPS-II, MIPS32, MIPS32R2, MIPS32R5 (32bit "old" ISAs)
>> Series2: MIPS-III, MIPS64, MIPS64R2, MIPS64R5 (64bit "old" ISAs)
>>
>> Series3: MIPS32R6 (32bit "new" ISAs)
>> Series4: MIPS64R6 (64bit "new" ISAs)
>
> Something like that, I'm starting by converting the messier leaves
> first, so the R6 and ASEs. My approach is from your "series4" to
> "series1" last.
>
> Regards,
>
> Phil.
>
- [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Richard Henderson, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper,
Philippe Mathieu-Daudé <=
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
[PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 07/24] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/15