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[PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handle
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers |
Date: |
Fri, 5 Mar 2021 17:21:03 +0100 |
The ISD MemoryRegion is implemented for 32-bit accesses.
Simplify it by setting the MemoryRegionOps::impl min/max
access size fields.
Since the region is registered with a size of 0x1000 bytes,
we can remove the hwaddr mask.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 6eb73e77057..99b1690af19 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -385,13 +385,12 @@ static void gt64120_writel(void *opaque, hwaddr addr,
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
- uint32_t saddr;
+ uint32_t saddr = addr >> 2;
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
- saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@@ -695,9 +694,8 @@ static uint64_t gt64120_readl(void *opaque,
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
- uint32_t saddr;
+ uint32_t saddr = addr >> 2;
- saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@@ -976,6 +974,10 @@ static const MemoryRegionOps isd_mem_ops = {
.read = gt64120_readl,
.write = gt64120_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
--
2.26.2
- [PATCH 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers,
Philippe Mathieu-Daudé <=
- [PATCH 1/6] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2021/03/05
- Re: [PATCH 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/09