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From: | BALATON Zoltan |
Subject: | Re: [PATCH 0/6] hw/mips/gt64120: Minor fixes |
Date: | Tue, 9 Mar 2021 15:04:03 +0100 (CET) |
On Tue, 9 Mar 2021, Philippe Mathieu-Daudé wrote:
Hi Zoltan, On 3/5/21 5:21 PM, Philippe Mathieu-Daudé wrote:Trivial fixes extracted from another series which became too big, so I prefer to send them in a previous step.I just realized I meant to Cc you on this series but forgot :/ As this model is pretty close to your MV64361 one, and this series is trivial, do you mind reviewing it? It shouldn't take more than 5min I hope ;)
Hello,I've noticed this patch series and considered reviewing it but could not do it in five minutes and I've lost it since. Can you forward it to me again so I can reply to the patches? (It's been a while I've written the mv64361 model so I may need to check datasheets again.)
Regards, BALATON Zoltan
Thanks, Phil.Philippe Mathieu-Daudé (6): hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats hw/mips/gt64xxx: Rename trace events related to interrupt registers hw/mips/gt64xxx: Trace accesses to ISD registers hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole hw/mips/gt64xxx_pci.c | 67 +++++++++++++++++++++++++++---------------- hw/mips/malta.c | 7 ----- hw/mips/trace-events | 6 ++-- 3 files changed, 47 insertions(+), 33 deletions(-)
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