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[PATCH 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers |
Date: |
Fri, 5 Mar 2021 17:21:06 +0100 |
Trace all accesses to Internal Space Decode (ISD) registers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 2 ++
hw/mips/trace-events | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 9a12d00d1e1..43349d6837d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -387,6 +387,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t saddr = addr >> 2;
+ trace_gt64120_write(addr, val);
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
@@ -966,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque,
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
+ trace_gt64120_read(addr, val);
return val;
}
diff --git a/hw/mips/trace-events b/hw/mips/trace-events
index b7e934c3933..13ee731a488 100644
--- a/hw/mips/trace-events
+++ b/hw/mips/trace-events
@@ -1,4 +1,6 @@
# gt64xxx_pci.c
+gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64"
value:0x%08" PRIx64
+gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64"
value:0x%08" PRIx64
gt64120_read_intreg(const char *regname, unsigned size, uint64_t value)
"gt64120 read %s size:%u value:0x%08" PRIx64
gt64120_write_intreg(const char *regname, unsigned size, uint64_t value)
"gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t
to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08"
PRIx64 "@0x%08" PRIx64
--
2.26.2
- [PATCH 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 2/6] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 1/6] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 3/6] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 4/6] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/05
- [PATCH 5/6] hw/mips/gt64xxx: Trace accesses to ISD registers,
Philippe Mathieu-Daudé <=
- [PATCH 6/6] hw/mips/gt64xxx: Let the GT64120 manage the lower 512MiB hole, Philippe Mathieu-Daudé, 2021/03/05
- Re: [PATCH 0/6] hw/mips/gt64120: Minor fixes, Philippe Mathieu-Daudé, 2021/03/09