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[PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and
From: |
Peter Maydell |
Subject: |
[PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI |
Date: |
Fri, 5 Mar 2021 17:15:02 +0000 |
On the MPS2 boards, the first 32 interrupt lines are entirely
internal to the SSE; interrupt lines for devices outside the SSE
start at 32. In the application notes that document each FPGA image,
the interrupt wiring is documented from the point of view of the CPU,
so '0' is the first of the SSE's interrupts and the devices in the
FPGA image itself are '32' and up: so the UART 0 Receive interrupt is
32, the SPI #0 interrupt is 51, and so on.
Within our implementation, because the external interrupts must be
connected to the EXP_IRQ[0...n] lines of the SSE object, we made the
get_sse_irq_in() function take an irqno whose values start at 0 for
the first FPGA device interrupt. In this numbering scheme the UART 0
Receive interrupt is 0, the SPI #0 interrupt is 19, and so on.
The result of these two different numbering schemes has been that
half of the devices were wired up to the wrong IRQs: the UART IRQs
are wired up correctly, but the DMA and SPI devices were passing
start-at-32 values to get_sse_irq_in() and so being mis-connected.
Fix the bug by making get_sse_irq_in() take values specified with the
same scheme that the hardware manuals use, to avoid confusion.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-12-peter.maydell@linaro.org
---
hw/arm/mps2-tz.c | 24 +++++++++++++++++-------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index eea9a71ddc0..b9b1351fa74 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -139,11 +139,21 @@ static void make_ram_alias(MemoryRegion *mr, const char
*name,
static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno)
{
- /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */
+ /*
+ * Return a qemu_irq which will signal IRQ n to all CPUs in the
+ * SSE. The irqno should be as the CPU sees it, so the first
+ * external-to-the-SSE interrupt is 32.
+ */
MachineClass *mc = MACHINE_GET_CLASS(mms);
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
- assert(irqno < mmc->numirq);
+ assert(irqno >= 32 && irqno < (mmc->numirq + 32));
+
+ /*
+ * Convert from "CPU irq number" (as listed in the FPGA image
+ * documentation) to the SSE external-interrupt number.
+ */
+ irqno -= 32;
if (mc->max_cpus > 1) {
return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0);
@@ -197,9 +207,9 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms,
void *opaque,
MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms);
CMSDKAPBUART *uart = opaque;
int i = uart - &mms->uart[0];
- int rxirqno = i * 2;
- int txirqno = i * 2 + 1;
- int combirqno = i + 10;
+ int rxirqno = i * 2 + 32;
+ int txirqno = i * 2 + 33;
+ int combirqno = i + 42;
SysBusDevice *s;
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
@@ -266,7 +276,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms,
void *opaque,
s = SYS_BUS_DEVICE(mms->lan9118);
sysbus_realize_and_unref(s, &error_fatal);
- sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
+ sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48));
return sysbus_mmio_get_region(s, 0);
}
@@ -507,7 +517,7 @@ static void mps2tz_common_init(MachineState *machine)
&error_fatal);
qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal);
qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0,
- get_sse_irq_in(mms, 15));
+ get_sse_irq_in(mms, 47));
/* Most of the devices in the FPGA are behind Peripheral Protection
* Controllers. The required order for initializing things is:
--
2.20.1
- [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524, (continued)
- [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524, Peter Maydell, 2021/03/05
- [PULL 46/49] hw/arm/mps2-tz: Stub out USB controller for mps3-an524, Peter Maydell, 2021/03/05
- [PULL 38/49] hw/arm/mps2-tz: Move device IRQ info to data structures, Peter Maydell, 2021/03/05
- [PULL 43/49] hw/arm/mps2-tz: Support ROMs as well as RAMs, Peter Maydell, 2021/03/05
- [PULL 44/49] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo, Peter Maydell, 2021/03/05
- [PULL 49/49] hw/arm/mps2: Update old infocenter.arm.com URLs, Peter Maydell, 2021/03/05
- [PULL 47/49] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524, Peter Maydell, 2021/03/05
- [PULL 40/49] hw/arm/mps2-tz: Allow boards to have different PPCInfo data, Peter Maydell, 2021/03/05
- [PULL 45/49] hw/arm/mps2-tz: Add new mps3-an524 board, Peter Maydell, 2021/03/05
- [PULL 33/49] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type, Peter Maydell, 2021/03/05
- [PULL 36/49] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI,
Peter Maydell <=
- [PULL 48/49] docs/system/arm/mps2.rst: Document the new mps3-an524 board, Peter Maydell, 2021/03/05
- [PULL 25/49] hw/display/tcx: Drop unnecessary code for handling BGR format outputs, Peter Maydell, 2021/03/05
- [PULL 42/49] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data, Peter Maydell, 2021/03/05
- [PULL 39/49] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs, Peter Maydell, 2021/03/05
- [PULL 41/49] hw/arm/mps2-tz: Make RAM arrangement board-specific, Peter Maydell, 2021/03/05
- Re: [PULL 00/49] target-arm queue, no-reply, 2021/03/05