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[PULL 46/54] tests/qtest/sse-timer-test: Test counter scaling changes
From: |
Peter Maydell |
Subject: |
[PULL 46/54] tests/qtest/sse-timer-test: Test counter scaling changes |
Date: |
Mon, 8 Mar 2021 17:32:36 +0000 |
Test that when we change the scaling of the system counter that the
system timer responds appropriately.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
tests/qtest/sse-timer-test.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/tests/qtest/sse-timer-test.c b/tests/qtest/sse-timer-test.c
index f4f6704b308..a65d7542d51 100644
--- a/tests/qtest/sse-timer-test.c
+++ b/tests/qtest/sse-timer-test.c
@@ -189,6 +189,37 @@ static void test_timer(void)
g_assert_cmpuint(readl(TIMER_BASE + CNTP_AIVAL_HI), ==, 0x42);
}
+static void test_timer_scale_change(void)
+{
+ /*
+ * Test that the timer responds correctly to counter
+ * scaling changes while it has an active timer.
+ */
+ reset_counter_and_timer();
+ /* Give ourselves access to the timer, and enable the counter and timer */
+ writel(PERIPHNSPPC0, 1);
+ writel(COUNTER_BASE + CNTCR, 1);
+ writel(TIMER_BASE + CNTP_CTL, 1);
+ /* Set the CompareValue to 4000 ticks */
+ writel(TIMER_BASE + CNTP_CVAL_LO, 4000);
+ writel(TIMER_BASE + CNTP_CVAL_HI, 0);
+ /* Advance halfway and check ISTATUS is not set */
+ clock_step_ticks(2000);
+ g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
+ /* Reprogram the counter to run at 1/16th speed */
+ writel(COUNTER_BASE + CNTCR, 0);
+ writel(COUNTER_BASE + CNTSCR, 0x00100000); /* 1/16th normal speed */
+ writel(COUNTER_BASE + CNTCR, 5); /* EN, SCEN */
+ /* Advance to where the timer would have fired and check it has not */
+ clock_step_ticks(2000);
+ g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
+ /* Advance to where the timer must fire at the new clock rate */
+ clock_step_ticks(29996);
+ g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 1);
+ clock_step_ticks(4);
+ g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 5);
+}
+
int main(int argc, char **argv)
{
int r;
@@ -199,6 +230,7 @@ int main(int argc, char **argv)
qtest_add_func("/sse-timer/counter", test_counter);
qtest_add_func("/sse-timer/timer", test_timer);
+ qtest_add_func("/sse-timer/timer-scale-change", test_timer_scale_change);
r = g_test_run();
--
2.20.1
- [PULL 36/54] hw/arm/mps2-tz: Make UART overflow IRQ board-specific, (continued)
- [PULL 36/54] hw/arm/mps2-tz: Make UART overflow IRQ board-specific, Peter Maydell, 2021/03/08
- [PULL 35/54] hw/arm/armsse: Add SSE-300 support, Peter Maydell, 2021/03/08
- [PULL 40/54] hw/arm/mps2-tz: Support running APB peripherals on different clock, Peter Maydell, 2021/03/08
- [PULL 42/54] hw/arm/mps2-tz: Add new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 43/54] docs/system/arm/mps2.rst: Document the new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 41/54] hw/arm/mps2-tz: Make initsvtor0 setting board-specific, Peter Maydell, 2021/03/08
- [PULL 37/54] hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate, Peter Maydell, 2021/03/08
- [PULL 45/54] tests/qtest/sse-timer-test: Test the system timer, Peter Maydell, 2021/03/08
- [PULL 50/54] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI, Peter Maydell, 2021/03/08
- [PULL 47/54] target/arm: Restrict v7A TCG cpus to TCG accel, Peter Maydell, 2021/03/08
- [PULL 46/54] tests/qtest/sse-timer-test: Test counter scaling changes,
Peter Maydell <=
- [PULL 53/54] hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_, Peter Maydell, 2021/03/08
- [PULL 52/54] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips, Peter Maydell, 2021/03/08
- [PULL 49/54] hw/arm: xlnx-zynqmp: Clean up coding convention issues, Peter Maydell, 2021/03/08
- [PULL 54/54] hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt(), Peter Maydell, 2021/03/08
- [PULL 48/54] hw/dma: Implement a Xilinx CSU DMA model, Peter Maydell, 2021/03/08
- [PULL 51/54] hw/ssi: xilinx_spips: Clean up coding convention issues, Peter Maydell, 2021/03/08
- Re: [PULL 00/54] target-arm queue, no-reply, 2021/03/08