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[PULL 49/54] hw/arm: xlnx-zynqmp: Clean up coding convention issues
From: |
Peter Maydell |
Subject: |
[PULL 49/54] hw/arm: xlnx-zynqmp: Clean up coding convention issues |
Date: |
Mon, 8 Mar 2021 17:32:39 +0000 |
From: Xuzhou Cheng <xuzhou.cheng@windriver.com>
There are some coding convention warnings in xlnx-zynqmp.c and
xlnx-zynqmp.h, as reported by:
$ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h
$ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-zynqmp.h | 3 ++-
hw/arm/xlnx-zynqmp.c | 9 ++++++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 0678b419a23..c83ef23e92d 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -60,7 +60,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_GIC_REGIONS 6
-/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
+/*
+ * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
* aligned address in the 64k region. To implement each GIC region needs a
* number of memory region aliases.
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 46030c1ef81..e2056a764e2 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -301,11 +301,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
ram_size = memory_region_size(s->ddr_ram);
- /* Create the DDR Memory Regions. User friendly checks should happen at
+ /*
+ * Create the DDR Memory Regions. User friendly checks should happen at
* the board level
*/
if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) {
- /* The RAM size is above the maximum available for the low DDR.
+ /*
+ * The RAM size is above the maximum available for the low DDR.
* Create the high DDR memory region as well.
*/
assert(ram_size <= XLNX_ZYNQMP_MAX_RAM_SIZE);
@@ -521,7 +523,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error
**errp)
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sdhci[i]);
Object *sdhci = OBJECT(&s->sdhci[i]);
- /* Compatible with:
+ /*
+ * Compatible with:
* - SD Host Controller Specification Version 3.00
* - SDIO Specification Version 3.0
* - eMMC Specification Version 4.51
--
2.20.1
- [PULL 42/54] hw/arm/mps2-tz: Add new mps3-an547 board, (continued)
- [PULL 42/54] hw/arm/mps2-tz: Add new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 43/54] docs/system/arm/mps2.rst: Document the new mps3-an547 board, Peter Maydell, 2021/03/08
- [PULL 41/54] hw/arm/mps2-tz: Make initsvtor0 setting board-specific, Peter Maydell, 2021/03/08
- [PULL 37/54] hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate, Peter Maydell, 2021/03/08
- [PULL 45/54] tests/qtest/sse-timer-test: Test the system timer, Peter Maydell, 2021/03/08
- [PULL 50/54] hw/arm: xlnx-zynqmp: Connect a Xilinx CSU DMA module for QSPI, Peter Maydell, 2021/03/08
- [PULL 47/54] target/arm: Restrict v7A TCG cpus to TCG accel, Peter Maydell, 2021/03/08
- [PULL 46/54] tests/qtest/sse-timer-test: Test counter scaling changes, Peter Maydell, 2021/03/08
- [PULL 53/54] hw/timer/renesas_tmr: Prefix constants for CSS values with CSS_, Peter Maydell, 2021/03/08
- [PULL 52/54] hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips, Peter Maydell, 2021/03/08
- [PULL 49/54] hw/arm: xlnx-zynqmp: Clean up coding convention issues,
Peter Maydell <=
- [PULL 54/54] hw/timer/renesas_tmr: Fix use of uninitialized data in read_tcnt(), Peter Maydell, 2021/03/08
- [PULL 48/54] hw/dma: Implement a Xilinx CSU DMA model, Peter Maydell, 2021/03/08
- [PULL 51/54] hw/ssi: xilinx_spips: Clean up coding convention issues, Peter Maydell, 2021/03/08
- Re: [PULL 00/54] target-arm queue, no-reply, 2021/03/08