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[PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu() |
Date: |
Sat, 13 Mar 2021 20:48:13 +0100 |
In the next commit we'll make decode_opc_mxu() match decodetree
prototype by returning a boolean. First pass ctx->opcode as an
argument.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9c06a0df814..8ab0a96a340 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25780,17 +25780,17 @@ static void decode_opc_mxu__pool19(DisasContext *ctx)
/*
* Main MXU decoding function
*/
-static void decode_opc_mxu(DisasContext *ctx)
+static void decode_opc_mxu(DisasContext *ctx, uint32_t insn)
{
- uint32_t opcode = extract32(ctx->opcode, 0, 6);
+ uint32_t opcode = extract32(insn, 0, 6);
if (opcode == OPC__MXU_MUL) {
uint32_t rs, rt, rd, op1;
- rs = extract32(ctx->opcode, 21, 5);
- rt = extract32(ctx->opcode, 16, 5);
- rd = extract32(ctx->opcode, 11, 5);
- op1 = MASK_SPECIAL2(ctx->opcode);
+ rs = extract32(insn, 21, 5);
+ rt = extract32(insn, 16, 5);
+ rd = extract32(insn, 11, 5);
+ op1 = MASK_SPECIAL2(insn);
gen_arith(ctx, op1, rd, rs, rt);
@@ -26995,7 +26995,7 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
#endif
#if !defined(TARGET_MIPS64)
if (ctx->insn_flags & ASE_MXU) {
- decode_opc_mxu(ctx);
+ decode_opc_mxu(ctx, ctx->opcode);
break;
}
#endif
--
2.26.2
- [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), (continued)
- [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 06/27] target/mips/meson: Introduce mips_tcg source set, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 08/27] target/mips: Rewrite complex ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu(),
Philippe Mathieu-Daudé <=
- [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 14/27] target/mips: Rename decode_opc_mxu() as decode_ase_mxu(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 17/27] target/mips: Introduce mxu_translate_init() helper, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible, Philippe Mathieu-Daudé, 2021/03/13