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[PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL |
Date: |
Sat, 13 Mar 2021 20:48:14 +0100 |
We already have a macro and definition to extract / check
the Special2 MUL opcode. Use it instead of the unnecessary
OPC__MXU_MUL macro.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ab0a96a340..ad09321de84 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1464,7 +1464,6 @@ enum {
*/
enum {
- OPC__MXU_MUL = 0x02,
OPC_MXU__POOL00 = 0x03,
OPC_MXU_D16MUL = 0x08,
OPC_MXU_D16MAC = 0x0A,
@@ -25784,7 +25783,7 @@ static void decode_opc_mxu(DisasContext *ctx, uint32_t
insn)
{
uint32_t opcode = extract32(insn, 0, 6);
- if (opcode == OPC__MXU_MUL) {
+ if (MASK_SPECIAL2(insn) == OPC_MUL) {
uint32_t rs, rt, rd, op1;
rs = extract32(insn, 21, 5);
--
2.26.2
- [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, (continued)
- [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 06/27] target/mips/meson: Introduce mips_tcg source set, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 08/27] target/mips: Rewrite complex ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL,
Philippe Mathieu-Daudé <=
- [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 14/27] target/mips: Rename decode_opc_mxu() as decode_ase_mxu(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 17/27] target/mips: Introduce mxu_translate_init() helper, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 21/27] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/13