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[PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup
From: |
Taylor Simpson |
Subject: |
[PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup |
Date: |
Wed, 31 Mar 2021 22:53:13 -0500 |
Simplify TCG generation of hex_reg_written
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 7481f4c..87f5d92 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -35,7 +35,6 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
{
- TCGv one = tcg_const_tl(1);
TCGv zero = tcg_const_tl(0);
TCGv slot_mask = tcg_temp_new();
@@ -43,12 +42,17 @@ static inline void gen_log_predicated_reg_write(int rnum,
TCGv val, int slot)
tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
val, hex_new_value[rnum]);
#if HEX_DEBUG
- /* Do this so HELPER(debug_commit_end) will know */
- tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
- one, hex_reg_written[rnum]);
+ /*
+ * Do this so HELPER(debug_commit_end) will know
+ *
+ * Note that slot_mask indicates the value is not written
+ * (i.e., slot was cancelled), so we create a true/false value before
+ * or'ing with hex_reg_written[rnum].
+ */
+ tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
+ tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
#endif
- tcg_temp_free(one);
tcg_temp_free(zero);
tcg_temp_free(slot_mask);
}
--
2.7.4
- [PATCH v2 00/21] Hexagon (target/hexagon) update, Taylor Simpson, 2021/03/31
- [PATCH v2 14/21] Hexagon (target/hexagon) add A5_ACS (vacsh), Taylor Simpson, 2021/03/31
- [PATCH v2 10/21] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn, Taylor Simpson, 2021/03/31
- [PATCH v2 02/21] Hexagon (target/hexagon) remove unnecessary inline directives, Taylor Simpson, 2021/03/31
- [PATCH v2 07/21] Hexagon (target/hexagon) remove unused carry_from_add64 function, Taylor Simpson, 2021/03/31
- [PATCH v2 06/21] Hexagon (target/hexagon) change variables from int to bool when appropriate, Taylor Simpson, 2021/03/31
- [PATCH v2 11/21] Hexagon (target/hexagon) use softfloat for float-to-int conversions, Taylor Simpson, 2021/03/31
- [PATCH v2 13/21] Hexagon (target/hexagon) add F2_sfinvsqrta, Taylor Simpson, 2021/03/31
- [PATCH v2 03/21] Hexagon (target/hexagon) use env_archcpu and env_cpu, Taylor Simpson, 2021/03/31
- [PATCH v2 04/21] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN, Taylor Simpson, 2021/03/31
- [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup,
Taylor Simpson <=
- [PATCH v2 05/21] Hexagon (target/hexagon) decide if pred has been written at TCG gen time, Taylor Simpson, 2021/03/31
- [PATCH v2 08/21] Hexagon (target/hexagon) change type of softfloat_roundingmodes, Taylor Simpson, 2021/03/31
- [PATCH v2 09/21] Hexagon (target/hexagon) use softfloat default NaN and tininess, Taylor Simpson, 2021/03/31
- [PATCH v2 15/21] Hexagon (target/hexagon) add A6_vminub_RdP, Taylor Simpson, 2021/03/31
- [PATCH v2 19/21] Hexagon (target/hexagon) load and unpack bytes instructions, Taylor Simpson, 2021/03/31
- [PATCH v2 20/21] Hexagon (target/hexagon) load into shifted register instructions, Taylor Simpson, 2021/03/31
- [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing, Taylor Simpson, 2021/03/31
- [PATCH v2 18/21] Hexagon (target/hexagon) bit reverse (brev) addressing, Taylor Simpson, 2021/03/31
- [PATCH v2 21/21] Hexagon (target/hexagon) CABAC decode bin, Taylor Simpson, 2021/03/31
- [PATCH v2 16/21] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c, Taylor Simpson, 2021/03/31