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Re: [PATCH v2 17/23] target/riscv: Remove dead code after exception
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 17/23] target/riscv: Remove dead code after exception |
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Date: |
Wed, 13 Oct 2021 07:35:20 +1000 |
On Wed, Oct 13, 2021 at 2:35 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We have already set DISAS_NORETURN in generate_exception,
> which makes the exit_tb unreachable.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
> b/target/riscv/insn_trans/trans_privileged.c.inc
> index 32312be202..a7afcb15ce 100644
> --- a/target/riscv/insn_trans/trans_privileged.c.inc
> +++ b/target/riscv/insn_trans/trans_privileged.c.inc
> @@ -22,8 +22,6 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
> {
> /* always generates U-level ECALL, fixed in do_interrupt handler */
> generate_exception(ctx, RISCV_EXCP_U_ECALL);
> - exit_tb(ctx); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> return true;
> }
>
> @@ -60,13 +58,11 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
> post = opcode_at(&ctx->base, post_addr);
> }
>
> - if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
> + if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
> generate_exception(ctx, RISCV_EXCP_SEMIHOST);
> } else {
> generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
> }
> - exit_tb(ctx); /* no chaining */
> - ctx->base.is_jmp = DISAS_NORETURN;
> return true;
> }
>
> --
> 2.25.1
>
>
- [PATCH v2 09/23] target/i386: Drop check for singlestep_enabled, (continued)
- [PATCH v2 09/23] target/i386: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 11/23] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP, Richard Henderson, 2021/10/12
- [PATCH v2 13/23] target/mips: Fix single stepping, Richard Henderson, 2021/10/12
- [PATCH v2 15/23] target/openrisc: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 10/23] target/m68k: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 12/23] target/microblaze: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 14/23] target/mips: Drop exit checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 17/23] target/riscv: Remove dead code after exception, Richard Henderson, 2021/10/12
- Re: [PATCH v2 17/23] target/riscv: Remove dead code after exception,
Alistair Francis <=
- [PATCH v2 18/23] target/riscv: Remove exit_tb and lookup_and_goto_ptr, Richard Henderson, 2021/10/12
- [PATCH v2 16/23] target/ppc: Drop exit checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 21/23] target/sh4: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 22/23] target/tricore: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 19/23] target/rx: Drop checks for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 20/23] target/s390x: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12
- [PATCH v2 23/23] target/xtensa: Drop check for singlestep_enabled, Richard Henderson, 2021/10/12