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Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing g
From: |
Philipp Tomsich |
Subject: |
Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci |
Date: |
Wed, 13 Oct 2021 15:49:17 +0200 |
On Wed, 13 Oct 2021 at 15:44, Vincent Palatin <vpalatin@rivosinc.com> wrote:
>
> On Wed, Oct 13, 2021 at 3:13 PM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > I had a much simpler version initially (using 3 x mask/shift/or, for
> > 12 instructions after setup of constants), but took up the suggestion
> > to optimize based on haszero(v)...
> > Indeed this appears to not do what we expect, when there's only 0x01
> > set in a byte.
> >
> > The less optimized form, with a single constant, that would still do
> > what we want is:
> > /* set high-bit for non-zero bytes */
> > constant = dup_const_tl(MO_8, 0x7f);
> > tmp = v & constant; // AND
> > tmp += constant; // ADD
> > tmp |= v; // OR
> > /* extract high-bit to low-bit, for each word */
> > tmp &= ~constant; // ANDC
> > tmp >>= 7; // SHR
> > /* multiply with 0xff to populate entire byte where the low-bit is set */
> > tmp *= 0xff; // MUL
> >
> > I'll submit a patch with this one later today, once I had a chance to
> > pass this through a full test.
>
>
> Thanks for the insight.
>
> I have tried it, implemented as:
> ```
> static void gen_orc_b(TCGv ret, TCGv source1)
> {
> TCGv tmp = tcg_temp_new();
> TCGv constant = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
>
> /* set high-bit for non-zero bytes */
> tcg_gen_and_tl(tmp, source1, constant);
> tcg_gen_add_tl(tmp, tmp, constant);
> tcg_gen_or_tl(tmp, tmp, source1);
> /* extract high-bit to low-bit, for each word */
> tcg_gen_andc_tl(tmp, tmp, constant);
> tcg_gen_shri_tl(tmp, tmp, 7);
>
> /* Replicate the lsb of each byte across the byte. */
> tcg_gen_muli_tl(ret, tmp, 0xff);
>
> tcg_temp_free(tmp);
> }
> ```
>
> It does pass my own test sequences.
I am running it against SPEC at the moment, using optimized
strlen/strcpy/strcmp functions using orc.b.
The verdict on that should be available later today...
Philipp.
- [PULL 05/26] target/riscv: Reassign instructions to the Zba-extension, (continued)
- [PULL 05/26] target/riscv: Reassign instructions to the Zba-extension, Alistair Francis, 2021/10/07
- [PULL 06/26] target/riscv: Remove the W-form instructions from Zbs, Alistair Francis, 2021/10/07
- [PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Alistair Francis, 2021/10/07
- [PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension, Alistair Francis, 2021/10/07
- [PULL 09/26] target/riscv: Add instructions of the Zbc-extension, Alistair Francis, 2021/10/07
- [PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension, Alistair Francis, 2021/10/07
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Alistair Francis, 2021/10/07
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci,
Philipp Tomsich <=
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vineet Gupta, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Richard Henderson, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
- [PATCH v1A] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
- [PATCH v1B] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro, Alistair Francis, 2021/10/07
[PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi, Alistair Francis, 2021/10/07
[PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Alistair Francis, 2021/10/07
[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs]), Alistair Francis, 2021/10/07
[PULL 16/26] disas/riscv: Add Zb[abcs] instructions, Alistair Francis, 2021/10/07