Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing g

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Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing g

From:	Richard Henderson
Subject:	Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Date:	Wed, 13 Oct 2021 09:51:21 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/13/21 9:20 AM, Vineet Gupta wrote:

off topic but relates, for Zb (and similar things in the future) whats the strategy forchange management/discovery. I understand you can hardcode things for quick test, but fora proper glibc implementation this would be an IFUNC but there seems to be noarchitectural way per spec (for software/kernel) to discover this.

Since the architecture restricted access to these CSRs, you do have to coordinate with thekernel.

There is an AT_HWCAP value that is given to userland, but it is currently masked to onlyprovide a few of the MISA bits. This will need to be extended for both V and Zb. Itdoesn't help that Zb has been split into lots of smaller extensions, which (if donesimplistically) will quickly consume all of the bits within AT_HWCAP.

So: I strongly suggest that RISC-V spend a few moments considering a way to represent thisthat will easily support the myriad extensions. One possibility is to add more AT_*entries straight away -- AT_HWCAP_ZB, which contains one bit for all of the Zb[abcs]extensions. Possibly set the "main" AT_HWCAP "b" bit if Zb is present at some minimal level.

Same issue is with building linux kernel with Zb - how do we make sure that hardware/simsupports Zb when running corresponding software.


On the kernel side this is easier -- read the CSRs then patch the kernel.
There are existing ways to manage this sort of thing.


r~

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[PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), (continued)
- [PULL 07/26] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B), Alistair Francis, 2021/10/07
- [PULL 08/26] target/riscv: Reassign instructions to the Zbs-extension, Alistair Francis, 2021/10/07
- [PULL 09/26] target/riscv: Add instructions of the Zbc-extension, Alistair Francis, 2021/10/07
- [PULL 10/26] target/riscv: Reassign instructions to the Zbb-extension, Alistair Francis, 2021/10/07
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Alistair Francis, 2021/10/07
  - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vineet Gupta, 2021/10/13
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Richard Henderson <=
    - Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
    - [PATCH v1A] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
    - [PATCH v1B] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
- [PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro, Alistair Francis, 2021/10/07
- [PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi, Alistair Francis, 2021/10/07
- [PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Alistair Francis, 2021/10/07
- [PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs]), Alistair Francis, 2021/10/07
- [PULL 16/26] disas/riscv: Add Zb[abcs] instructions, Alistair Francis, 2021/10/07
- [PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty(), Alistair Francis, 2021/10/07
- [PULL 18/26] hw/char: ibex_uart: Register device in 'input' category, Alistair Francis, 2021/10/07

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