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[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro
From: |
Alistair Francis |
Subject: |
[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro |
Date: |
Thu, 7 Oct 2021 16:47:37 +1000 |
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
With the changes to Zb[abcs], there's some encodings that are
different in RV64 and RV32 (e.g., for rev8 and zext.h). For these,
we'll need a helper macro allowing us to select on RV32, as well.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20210911140016.834071-13-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..b2d3444bc5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -337,6 +337,12 @@ EX_SH(12)
} \
} while (0)
+#define REQUIRE_32BIT(ctx) do { \
+ if (!is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_64BIT(ctx) do { \
if (is_32bit(ctx)) { \
return false; \
--
2.31.1
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, (continued)
- [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Alistair Francis, 2021/10/07
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vincent Palatin, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Vineet Gupta, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Richard Henderson, 2021/10/13
- Re: [PULL 11/26] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci, Philipp Tomsich, 2021/10/13
- [PATCH v1A] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
- [PATCH v1B] target/riscv: fix orc.b instruction in the Zbb extension, Vincent Palatin, 2021/10/13
[PULL 12/26] target/riscv: Add a REQUIRE_32BIT macro,
Alistair Francis <=
[PULL 13/26] target/riscv: Add rev8 instruction, removing grev/grevi, Alistair Francis, 2021/10/07
[PULL 14/26] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh, Alistair Francis, 2021/10/07
[PULL 15/26] target/riscv: Remove RVB (replaced by Zb[abcs]), Alistair Francis, 2021/10/07
[PULL 16/26] disas/riscv: Add Zb[abcs] instructions, Alistair Francis, 2021/10/07
[PULL 17/26] target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty(), Alistair Francis, 2021/10/07
[PULL 18/26] hw/char: ibex_uart: Register device in 'input' category, Alistair Francis, 2021/10/07
[PULL 19/26] hw/char: shakti_uart: Register device in 'input' category, Alistair Francis, 2021/10/07
[PULL 20/26] hw/char: sifive_uart: Register device in 'input' category, Alistair Francis, 2021/10/07
[PULL 21/26] hw/char/mchp_pfsoc_mmuart: Simplify MCHP_PFSOC_MMUART_REG definition, Alistair Francis, 2021/10/07
[PULL 24/26] hw/dma: sifive_pdma: Fix Control.claim bit detection, Alistair Francis, 2021/10/07