[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Re
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 |
Date: |
Mon, 18 Oct 2021 00:52:29 +0200 |
Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04,
MULT and MULTU opcodes:
The value of ac selects an accumulator numbered from 0 to 3.
When ac=0, this refers to the original HI/LO register pair of the
MIPS32 architecture.
In Release 6 of the MIPS Architecture, accumulators are eliminated
from MIPS32.
Ensure pre-Release 6 is restricted to HI/LO registers pair.
Fixes: 8b3698b2947 ("target/mips: Add emulation of DSP ASE for nanoMIPS - part
4")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/nanomips_translate.c.inc | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/mips/tcg/nanomips_translate.c.inc
b/target/mips/tcg/nanomips_translate.c.inc
index ccbcecad093..2c022a49f24 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1868,6 +1868,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext
*ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
+ if (acc || ctx->insn_flags & ISA_MIPS_R6) {
+ check_dsp_r2(ctx);
+ }
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);
@@ -1925,6 +1928,9 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext
*ctx, uint32_t opc,
TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i32 t3 = tcg_temp_new_i32();
+ if (acc || ctx->insn_flags & ISA_MIPS_R6) {
+ check_dsp_r2(ctx);
+ }
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
tcg_gen_trunc_tl_i32(t2, t0);
--
2.31.1
- [PULL 00/17] MIPS patches for 2021-10-18, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6,
Philippe Mathieu-Daudé <=
- [PULL 02/17] hw/mips/boston: Massage memory map information, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 04/17] hw/mips/boston: Add FDT generator, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch(), Philippe Mathieu-Daudé, 2021/10/17