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[PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() |
Date: |
Mon, 18 Oct 2021 00:52:34 +0200 |
Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-3-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index ee6424126f7..20036ae4968 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1650,7 +1650,7 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t
df, uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
- TCGv_i32 tdf = tcg_const_i32(df);
+ TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_SLDI_df:
@@ -1748,7 +1748,6 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t
df, uint32_t n)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
tcg_temp_free_i32(tn);
- tcg_temp_free_i32(tdf);
}
static void gen_msa_elm(DisasContext *ctx)
--
2.31.1
- [PULL 00/17] MIPS patches for 2021-10-18, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 02/17] hw/mips/boston: Massage memory map information, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 04/17] hw/mips/boston: Add FDT generator, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df(),
Philippe Mathieu-Daudé <=
- [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 14/17] via-ide: Set user_creatable to false, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 15/17] vt82c686: Move common code to via_isa_realize, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts, Philippe Mathieu-Daudé, 2021/10/17