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[PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5()
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5() |
Date: |
Mon, 18 Oct 2021 00:52:38 +0200 |
We already use sextract32(), use extract32() for completeness
instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211003175743.3738710-7-f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e107cad57ee..3ef912da6b8 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -473,15 +473,12 @@ static void gen_msa_i8(DisasContext *ctx)
static void gen_msa_i5(DisasContext *ctx)
{
#define MASK_MSA_I5(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
- uint8_t df = (ctx->opcode >> 21) & 0x3;
int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
- uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ uint8_t u5 = extract32(ctx->opcode, 16, 5);
- TCGv_i32 tdf = tcg_const_i32(df);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
+ TCGv_i32 tdf = tcg_const_i32(extract32(ctx->opcode, 21, 2));
+ TCGv_i32 twd = tcg_const_i32(extract32(ctx->opcode, 11, 5));
+ TCGv_i32 tws = tcg_const_i32(extract32(ctx->opcode, 6, 5));
TCGv_i32 timm = tcg_temp_new_i32();
tcg_gen_movi_i32(timm, u5);
--
2.31.1
- [PULL 00/17] MIPS patches for 2021-10-18, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 02/17] hw/mips/boston: Massage memory map information, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 04/17] hw/mips/boston: Add FDT generator, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5(),
Philippe Mathieu-Daudé <=
- [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn(), Philippe Mathieu-Daudé, 2021/10/17
- [PULL 14/17] via-ide: Set user_creatable to false, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 15/17] vt82c686: Move common code to via_isa_realize, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts, Philippe Mathieu-Daudé, 2021/10/17
- [PULL 17/17] via-ide: Avoid using isa_get_irq(), Philippe Mathieu-Daudé, 2021/10/17
- Re: [PULL 00/17] MIPS patches for 2021-10-18, Richard Henderson, 2021/10/18