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From: | Richard Henderson |
Subject: | Re: [PATCH 20/33] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) |
Date: | Sun, 24 Oct 2021 10:37:54 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a, + enum CPUMIPSMSADataFormat df_base, + void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_i32)) +{ + TCGv_i32 twd = tcg_const_i32(a->wd); + TCGv_i32 tws = tcg_const_i32(a->ws); + TCGv_i32 twt = tcg_const_i32(a->wt); + /* adjust df value for floating-point instruction */ + TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
I think it would be better to decode df completely in decodetree. E.g. %df_hw 21:1 !function=plus_1 @3rf_hw ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%df_hw %df_wd 21:1 !function=plus_2 @3rf_wd ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%df_wd Maybe I should get that !expression=(x+1) syntax going soon... r~
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