Re: [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree

[Richard Henderson]

On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/mips/tcg/msa.decode      |  2 ++
>   target/mips/tcg/msa_translate.c | 40 +++++++++++++++++++++++----------
>   2 files changed, 30 insertions(+), 12 deletions(-)
>
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 2997bfa24e3..e97490cf880 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -21,6 +21,7 @@
>   @ldst               ...... sa:s10 ws:5 wd:5 .... df:2       &msa_ldst
>   @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
>   @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
> +@2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
>   @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
>   @u5                 ...... ... df:2 sa:5  ws:5 wd:5 ......  &msa_ldst
>   @s5                 ...... ... df:2 sa:s5 ws:5 wd:5 ......  &msa_ldst
> @@ -76,6 +77,7 @@ BNZ                 010001 111 .. ..... ................    
> @bz
>     SRARI             011110 010 ....... ..... .....  001010  @bit
>     SRLRI             011110 011 ....... ..... .....  001010  @bit
>   
> +  FILL              011110 11000000 .. ..... .....  011110  @2r
>     FCLASS            011110 110010000 . ..... .....  011110  @2rf
>     FTRUNC_S          011110 110010001 . ..... .....  011110  @2rf
>     FTRUNC_U          011110 110010010 . ..... .....  011110  @2rf
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index c6a77381c0e..fc0b80f83ac 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -53,7 +53,6 @@ enum {
>       OPC_MSA_2R      = (0x18 << 21) | OPC_MSA_VEC,
>   
>       /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
> -    OPC_FILL_df     = (0x00 << 18) | OPC_MSA_2R,
>       OPC_PCNT_df     = (0x01 << 18) | OPC_MSA_2R,
>       OPC_NLOC_df     = (0x02 << 18) | OPC_MSA_2R,
>       OPC_NLZC_df     = (0x03 << 18) | OPC_MSA_2R,
> @@ -1844,17 +1843,6 @@ static void gen_msa_2r(DisasContext *ctx)
>       TCGv_i32 tws = tcg_const_i32(ws);
>   
>       switch (MASK_MSA_2R(ctx->opcode)) {
> -    case OPC_FILL_df:
> -#if !defined(TARGET_MIPS64)
> -        /* Double format valid only for MIPS64 */
> -        if (df == DF_DOUBLE) {
> -            gen_reserved_instruction(ctx);
> -            break;
> -        }
> -#endif
> -        gen_helper_msa_fill_df(cpu_env, tcg_constant_i32(df),
> -                               twd, tws); /* trs */
> -        break;
>       case OPC_NLOC_df:
>           switch (df) {
>           case DF_BYTE:
> @@ -1913,6 +1901,34 @@ static void gen_msa_2r(DisasContext *ctx)
>       tcg_temp_free_i32(tws);
>   }
>   
> +static bool trans_FILL(DisasContext *ctx, arg_msa_r *a)
> +{
> +    TCGv_i32 twd;
> +    TCGv_i32 tws;
> +    TCGv_i32 tdf;
> +
> +    if (!check_msa_access(ctx)) {
> +        return false;
> +    }
> +
> +    if (TARGET_LONG_BITS != 64 && a->df == DF_DOUBLE) {
> +        /* Double format valid only for MIPS64 */
> +        gen_reserved_instruction(ctx);
> +        return true;
> +    }

I expect this reserved check should be above the MSA is disabled check, within 
check_msa_access.

> +    twd = tcg_const_i32(a->wd);
> +    tws = tcg_const_i32(a->ws);

tcg_constant_i32.

r~