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[PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetr
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree |
Date: |
Sat, 23 Oct 2021 23:47:44 +0200 |
Convert instructions with an 8-bit immediate value and either
implicit data format or data format df to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 8 ++++
target/mips/tcg/msa_translate.c | 72 +++++++++------------------------
2 files changed, 26 insertions(+), 54 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 6347468a709..3dd07dced57 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -23,6 +23,7 @@
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
@i8_df ...... df:2 sa:s8 ws:5 wd:5 ...... &msa_ldst
+@i8 ...... .. sa:s8 ws:5 wd:5 ...... &msa_ldst df=0
@bit ...... ... df:7 ws:5 wd:5 ...... &msa_ldst sa=0
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
@@ -34,6 +35,13 @@ BZ 010001 110 .. ..... ................
@bz
BNZ 010001 111 .. ..... ................ @bz
{
+ ANDI 011110 00 ........ ..... ..... 000000 @i8
+ ORI 011110 01 ........ ..... ..... 000000 @i8
+ NORI 011110 10 ........ ..... ..... 000000 @i8
+ XORI 011110 11 ........ ..... ..... 000000 @i8
+ BMNZI 011110 00 ........ ..... ..... 000001 @i8
+ BMZI 011110 01 ........ ..... ..... 000001 @i8
+ BSELI 011110 10 ........ ..... ..... 000001 @i8
SHF 011110 .. ........ ..... ..... 000010 @i8_df
ADDVI 011110 000 .. ..... ..... ..... 000110 @u5
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 7cb078bfe92..2866687635d 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -24,9 +24,6 @@
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
enum {
- OPC_MSA_I8_00 = 0x00 | OPC_MSA,
- OPC_MSA_I8_01 = 0x01 | OPC_MSA,
- OPC_MSA_I8_02 = 0x02 | OPC_MSA,
OPC_MSA_3R_0D = 0x0D | OPC_MSA,
OPC_MSA_3R_0E = 0x0E | OPC_MSA,
OPC_MSA_3R_0F = 0x0F | OPC_MSA,
@@ -54,15 +51,6 @@ enum {
};
enum {
- /* I8 instruction */
- OPC_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
- OPC_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
- OPC_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
- OPC_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
- OPC_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
- OPC_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
- OPC_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
-
/* VEC/2R/2RF instruction */
OPC_AND_V = (0x00 << 21) | OPC_MSA_VEC,
OPC_OR_V = (0x01 << 21) | OPC_MSA_VEC,
@@ -418,50 +406,31 @@ static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
}
-static void gen_msa_i8(DisasContext *ctx)
+static bool trans_msa_i8(DisasContext *ctx, arg_msa_ldst *a,
+ void (*gen_msa_i8)(TCGv_ptr, TCGv_i32,
+ TCGv_i32, TCGv_i32))
{
-#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
- uint8_t i8 = (ctx->opcode >> 16) & 0xff;
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv_i32 tws = tcg_const_i32(a->ws);
+ TCGv_i32 timm = tcg_const_i32(a->sa);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 ti8 = tcg_const_i32(i8);
-
- switch (MASK_MSA_I8(ctx->opcode)) {
- case OPC_ANDI_B:
- gen_helper_msa_andi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_ORI_B:
- gen_helper_msa_ori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_NORI_B:
- gen_helper_msa_nori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_XORI_B:
- gen_helper_msa_xori_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMNZI_B:
- gen_helper_msa_bmnzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BMZI_B:
- gen_helper_msa_bmzi_b(cpu_env, twd, tws, ti8);
- break;
- case OPC_BSELI_B:
- gen_helper_msa_bseli_b(cpu_env, twd, tws, ti8);
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- break;
- }
+ gen_msa_i8(cpu_env, twd, tws, timm);
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(ti8);
+ tcg_temp_free_i32(timm);
+
+ return true;
}
+TRANS_MSA(ANDI, trans_msa_i8, gen_helper_msa_andi_b);
+TRANS_MSA(ORI, trans_msa_i8, gen_helper_msa_ori_b);
+TRANS_MSA(NORI, trans_msa_i8, gen_helper_msa_nori_b);
+TRANS_MSA(XORI, trans_msa_i8, gen_helper_msa_xori_b);
+TRANS_MSA(BMNZI, trans_msa_i8, gen_helper_msa_bmnzi_b);
+TRANS_MSA(BMZI, trans_msa_i8, gen_helper_msa_bmzi_b);
+TRANS_MSA(BSELI, trans_msa_i8, gen_helper_msa_bseli_b);
+
static bool trans_SHF(DisasContext *ctx, arg_msa_ldst *a)
{
TCGv_i32 tdf;
@@ -2113,11 +2082,6 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
}
switch (MASK_MSA_MINOR(opcode)) {
- case OPC_MSA_I8_00:
- case OPC_MSA_I8_01:
- case OPC_MSA_I8_02:
- gen_msa_i8(ctx);
- break;
case OPC_MSA_3R_0D:
case OPC_MSA_3R_0E:
case OPC_MSA_3R_0F:
--
2.31.1
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, (continued)
- [PATCH 09/33] target/mips: Introduce generic TRANS_CHECK() for decodetree helpers, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 10/33] target/mips: Extract df_extract() helper, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 11/33] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 12/33] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 13/33] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 14/33] target/mips: Convert MSA I8 instruction format to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH 15/33] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 16/33] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/23
- [PATCH 17/33] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/23