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[PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decod
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) |
Date: |
Wed, 27 Oct 2021 20:07:18 +0200 |
Convert 3-register operations to decodetree.
Since the 'data format' field is a constant value, use
tcg_constant_i32() instead of a TCG temporary.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 6 ++++++
target/mips/tcg/msa_translate.c | 29 +++++++++++++++++------------
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index f88ae234cca..7201b821ae0 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -31,6 +31,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
+@3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
@3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_i5
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_i5
@@ -86,6 +87,11 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ SLD 011110 000 .. ..... ..... ..... 010100 @3r
+ SPLAT 011110 001 .. ..... ..... ..... 010100 @3r
+
+ VSHF 011110 000 .. ..... ..... ..... 010101 @3r
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index f635b49c13c..c7ca629d684 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -48,15 +48,12 @@ enum {
OPC_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
OPC_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
OPC_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
- OPC_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
- OPC_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
OPC_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
OPC_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
OPC_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
OPC_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
OPC_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
OPC_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
- OPC_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
OPC_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
OPC_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
OPC_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -457,6 +454,23 @@ TRANS_MSA(SAT_U, trans_msa_bit,
gen_helper_msa_sat_u_df);
TRANS_MSA(SRARI, trans_msa_bit, gen_helper_msa_srari_df);
TRANS_MSA(SRLRI, trans_msa_bit, gen_helper_msa_srlri_df);
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+ gen_helper_piiii *gen_msa_3r_df)
+{
+ gen_msa_3r_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->wt));
+
+ return true;
+}
+
+TRANS_MSA(SLD, trans_msa_3r_df, gen_helper_msa_sld_df);
+TRANS_MSA(SPLAT, trans_msa_3r_df, gen_helper_msa_splat_df);
+
+TRANS_MSA(VSHF, trans_msa_3r_df, gen_helper_msa_vshf_df);
+
static void gen_msa_3r(DisasContext *ctx)
{
#define MASK_MSA_3R(op) (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
@@ -1207,12 +1221,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SLD_df:
- gen_helper_msa_sld_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_VSHF_df:
- gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBV_df:
switch (df) {
case DF_BYTE:
@@ -1245,9 +1253,6 @@ static void gen_msa_3r(DisasContext *ctx)
break;
}
break;
- case OPC_SPLAT_df:
- gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
switch (df) {
case DF_BYTE:
--
2.31.1
- [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree, (continued)
- [PATCH v2 15/32] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 16/32] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4),
Philippe Mathieu-Daudé <=
- [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27