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[PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to deco
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree |
Date: |
Wed, 27 Oct 2021 20:07:22 +0200 |
Convert instructions with an immediate element index
and data format df/n to decodetree.
Since the 'data format' and 'n' fields are constant values,
use tcg_constant_i32() instead of a TCG temporaries.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Return 'false' (not decoded) for invalid DF values (Richard)
---
target/mips/tcg/msa.decode | 8 +++++
target/mips/tcg/msa_translate.c | 53 +++++++++++++++++++++++++--------
2 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 985af71889e..e701e507bfc 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -20,7 +20,10 @@
&msa_i8 df wd ws sa
&msa_ldst df wd ws sa
&msa_bit df wd ws m
+&msa_elm_df df wd ws n
+%dfn_df 16:6 !function=msa_elm_df
+%dfn_n 16:6 !function=msa_elm_n
%dfm_df 16:7 !function=msa_bit_df
%dfm_m 16:7 !function=msa_bit_m
@@ -28,6 +31,7 @@
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_ldst
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
+@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df
df=%dfn_df n=%dfn_n
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
@@ -159,6 +163,10 @@ BNZ 010001 111 .. ..... ................
@bz
HSUB_S 011110 110.. ..... ..... ..... 010101 @3r
HSUB_U 011110 111.. ..... ..... ..... 010101 @3r
+ SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
+ SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
+
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
FCUN 011110 0001 . ..... ..... ..... 011010 @3rf
FCEQ 011110 0010 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index d846f72c72b..fabc7f5538b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -17,6 +17,8 @@
#include "fpu_helper.h"
#include "internal.h"
+static int msa_elm_n(DisasContext *ctx, int x);
+static int msa_elm_df(DisasContext *ctx, int x);
static int msa_bit_m(DisasContext *ctx, int x);
static int msa_bit_df(DisasContext *ctx, int x);
@@ -32,15 +34,12 @@ enum {
enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
- OPC_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
- OPC_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -97,6 +96,24 @@ static int msa_df_extract_df(DisasContext *ctx, int x, const
struct dfe *s)
return -1;
}
+static const struct dfe df_elm[] = {
+ /* Table 3.26 ELM Instruction Format */
+ [DF_BYTE] = {4, 2, 0b00},
+ [DF_HALF] = {3, 3, 0b100},
+ [DF_WORD] = {2, 4, 0b1100},
+ [DF_DOUBLE] = {1, 5, 0b11100}
+};
+
+static int msa_elm_n(DisasContext *ctx, int x)
+{
+ return msa_df_extract_val(ctx, x, df_elm);
+}
+
+static int msa_elm_df(DisasContext *ctx, int x)
+{
+ return msa_df_extract_df(ctx, x, df_elm);
+}
+
static const struct dfe df_bit[] = {
/* Table 3.28 BIT Instruction Format */
[DF_BYTE] = {3, 4, 0b1110},
@@ -528,6 +545,26 @@ static void gen_msa_elm_3e(DisasContext *ctx)
tcg_temp_free_i32(tsr);
}
+static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm_df *a,
+ gen_helper_piiii *gen_msa_elm_df)
+{
+ if (a->df < 0) {
+ return false;
+ }
+
+ gen_msa_elm_df(cpu_env,
+ tcg_constant_i32(a->df),
+ tcg_constant_i32(a->wd),
+ tcg_constant_i32(a->ws),
+ tcg_constant_i32(a->n));
+
+ return true;
+}
+
+TRANS_MSA(SLDI, trans_msa_elm_df, gen_helper_msa_sldi_df);
+TRANS_MSA(SPLATI, trans_msa_elm_df, gen_helper_msa_splati_df);
+TRANS_MSA(INSVE, trans_msa_elm_df, gen_helper_msa_insve_df);
+
static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
{
#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -537,18 +574,8 @@ static void gen_msa_elm_df(DisasContext *ctx, uint32_t df,
uint32_t n)
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tn = tcg_const_i32(n);
- TCGv_i32 tdf = tcg_constant_i32(df);
switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_SLDI_df:
- gen_helper_msa_sldi_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_SPLATI_df:
- gen_helper_msa_splati_df(cpu_env, tdf, twd, tws, tn);
- break;
- case OPC_INSVE_df:
- gen_helper_msa_insve_df(cpu_env, tdf, twd, tws, tn);
- break;
case OPC_COPY_S_df:
case OPC_COPY_U_df:
case OPC_INSERT_df:
--
2.31.1
- [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree, (continued)
- [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree,
Philippe Mathieu-Daudé <=
- [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 30/32] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 28/32] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 29/32] target/mips: Convert CTCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 32/32] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/10/27