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[PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decod
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) |
Date: |
Wed, 27 Oct 2021 20:07:20 +0200 |
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 40 +++++----------------------------
2 files changed, 9 insertions(+), 34 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index f6471b92fc7..19458f180f5 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -87,6 +87,9 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ BINSL 011110 110.. ..... ..... ..... 001101 @3r
+ BINSR 011110 111.. ..... ..... ..... 001101 @3r
+
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 5cc704c9ace..a5a5cc4bcac 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -81,12 +81,10 @@ enum {
OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
- OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
- OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
@@ -247,6 +245,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32);
#define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func)
+#define TRANS_DF_iii(NAME, trans_func, gen_func) \
+ TRANS_DF_x(iii, NAME, trans_func, gen_func)
+
#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
static gen_helper_piii * const NAME##_tab[4] = { \
gen_func##_h, gen_func##_w, gen_func##_d \
@@ -482,6 +483,9 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
return true;
}
+TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
+TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
+
TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
@@ -512,38 +516,6 @@ static void gen_msa_3r(DisasContext *ctx)
TCGv_i32 twt = tcg_const_i32(wt);
switch (MASK_MSA_3R(ctx->opcode)) {
- case OPC_BINSL_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
- case OPC_BINSR_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
- break;
- case DF_HALF:
- gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
- break;
- case DF_WORD:
- gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
- break;
- case DF_DOUBLE:
- gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
- break;
- }
- break;
case OPC_BCLR_df:
switch (df) {
case DF_BYTE:
--
2.31.1
- [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree, (continued)
- [PATCH v2 17/32] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 18/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 19/32] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 20/32] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 22/32] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4),
Philippe Mathieu-Daudé <=
- [PATCH v2 23/32] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4), Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 24/32] target/mips: Convert MSA ELM instruction format to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 26/32] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 25/32] target/mips: Convert MSA COPY_U opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 27/32] target/mips: Convert MSA MOVE.V opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 30/32] target/mips: Remove generic MSA opcode, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 31/32] target/mips: Remove one MSA unnecessary decodetree overlap group, Philippe Mathieu-Daudé, 2021/10/27
- [PATCH v2 28/32] target/mips: Convert CFCMSA opcode to decodetree, Philippe Mathieu-Daudé, 2021/10/27