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[PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on
From: |
Alistair Francis |
Subject: |
[PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on |
Date: |
Fri, 29 Oct 2021 17:08:13 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16fac64806..7d53125dbc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -562,6 +562,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_vext_version(env, vext_version);
}
+ if (cpu->cfg.ext_j) {
+ ext |= RVJ;
+ }
set_misa(env, env->misa_mxl, ext);
}
@@ -637,6 +640,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
--
2.31.1
- [PULL v2 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, (continued)
- [PULL v2 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/29
- [PULL v2 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/29
- [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/29
- [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/29
- [PULL v2 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/29
- [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/29
- [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/29
- [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/29
- [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on,
Alistair Francis <=
- [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS, Alistair Francis, 2021/10/29
- [PULL v2 16/18] target/riscv: remove force HS exception, Alistair Francis, 2021/10/29
- [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/29
- [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/29
- Re: [PULL v2 00/18] riscv-to-apply queue, Richard Henderson, 2021/10/29