[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS
From: |
Alistair Francis |
Subject: |
[PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS |
Date: |
Fri, 29 Oct 2021 17:08:14 +1000 |
From: Jose Martins <josemartins90@gmail.com>
VS interrupts (2, 6, 10) were not correctly forwarded to hs-mode when
not delegated in hideleg (which was not being taken into account). This
was mainly because hs level sie was not always considered enabled when
it should. The spec states that "Interrupts for higher-privilege modes,
y>x, are always globally enabled regardless of the setting of the global
yIE bit for the higher-privilege mode." and also "For purposes of
interrupt global enables, HS-mode is considered more privileged than
VS-mode, and VS-mode is considered more privileged than VU-mode". Also,
vs-level interrupts were not being taken into account unless V=1, but
should be unless delegated.
Finally, there is no need for a special case for to handle vs interrupts
as the current privilege level, the state of the global ie and of the
delegation registers should be enough to route all interrupts to the
appropriate privilege level in riscv_cpu_do_interrupt.
Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-2-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 28 ++++++++--------------------
1 file changed, 8 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 662228c238..5076580374 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -135,36 +135,24 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
#ifndef CONFIG_USER_ONLY
static int riscv_cpu_local_irq_pending(CPURISCVState *env)
{
- target_ulong irqs;
+ target_ulong virt_enabled = riscv_cpu_virt_enabled(env);
target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE);
target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE);
- target_ulong hs_mstatus_sie = get_field(env->mstatus_hs, MSTATUS_SIE);
- target_ulong pending = env->mip & env->mie &
- ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
- target_ulong vspending = (env->mip & env->mie &
- (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
+ target_ulong pending = env->mip & env->mie;
target_ulong mie = env->priv < PRV_M ||
(env->priv == PRV_M && mstatus_mie);
target_ulong sie = env->priv < PRV_S ||
(env->priv == PRV_S && mstatus_sie);
- target_ulong hs_sie = env->priv < PRV_S ||
- (env->priv == PRV_S && hs_mstatus_sie);
+ target_ulong hsie = virt_enabled || sie;
+ target_ulong vsie = virt_enabled && sie;
- if (riscv_cpu_virt_enabled(env)) {
- target_ulong pending_hs_irq = pending & -hs_sie;
-
- if (pending_hs_irq) {
- riscv_cpu_set_force_hs_excep(env, FORCE_HS_EXCEP);
- return ctz64(pending_hs_irq);
- }
-
- pending = vspending;
- }
-
- irqs = (pending & ~env->mideleg & -mie) | (pending & env->mideleg & -sie);
+ target_ulong irqs =
+ (pending & ~env->mideleg & -mie) |
+ (pending & env->mideleg & ~env->hideleg & -hsie) |
+ (pending & env->mideleg & env->hideleg & -vsie);
if (irqs) {
return ctz64(irqs); /* since non-zero */
--
2.31.1
- [PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function, (continued)
- [PULL v2 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/29
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/29
- [PULL v2 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/29
- [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/29
- [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/29
- [PULL v2 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/29
- [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/29
- [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/29
- [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/29
- [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/29
- [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS,
Alistair Francis <=
- [PULL v2 16/18] target/riscv: remove force HS exception, Alistair Francis, 2021/10/29
- [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/29
- [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/29
- Re: [PULL v2 00/18] riscv-to-apply queue, Richard Henderson, 2021/10/29