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[PULL v2 16/18] target/riscv: remove force HS exception
From: |
Alistair Francis |
Subject: |
[PULL v2 16/18] target/riscv: remove force HS exception |
Date: |
Fri, 29 Oct 2021 17:08:15 +1000 |
From: Jose Martins <josemartins90@gmail.com>
There is no need to "force an hs exception" as the current privilege
level, the state of the global ie and of the delegation registers should
be enough to route the interrupt to the appropriate privilege level in
riscv_cpu_do_interrupt. The is true for both asynchronous and
synchronous exceptions, specifically, guest page faults which must be
hardwired to zero hedeleg. As such the hs_force_except mechanism can be
removed.
Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-3-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 --
target/riscv/cpu_bits.h | 6 ------
target/riscv/cpu_helper.c | 26 +-------------------------
3 files changed, 1 insertion(+), 33 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 325908287d..0760c0af93 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -352,8 +352,6 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t
*buf, int reg);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
-void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index aa0bce4e06..9913fa9f77 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -444,12 +444,6 @@ typedef enum {
/* Virtulisation Register Fields */
#define VIRT_ONOFF 1
-/* This is used to save state for when we take an exception. If this is set
- * that means that we want to force a HS level exception (no matter what the
- * delegation is set to). This will occur for things such as a second level
- * page table fault.
- */
-#define FORCE_HS_EXCEP 2
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 5076580374..f30ff672f8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -270,24 +270,6 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
enable)
env->virt = set_field(env->virt, VIRT_ONOFF, enable);
}
-bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
-{
- if (!riscv_has_ext(env, RVH)) {
- return false;
- }
-
- return get_field(env->virt, FORCE_HS_EXCEP);
-}
-
-void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
-{
- if (!riscv_has_ext(env, RVH)) {
- return;
- }
-
- env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
-}
-
bool riscv_cpu_two_stage_lookup(int mmu_idx)
{
return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK;
@@ -1004,7 +986,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- bool force_hs_execp = riscv_cpu_force_hs_excep_enabled(env);
uint64_t s;
/* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide
@@ -1033,8 +1014,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
case RISCV_EXCP_INST_GUEST_PAGE_FAULT:
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
- force_hs_execp = true;
- /* fallthrough */
case RISCV_EXCP_INST_ADDR_MIS:
case RISCV_EXCP_INST_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
@@ -1093,8 +1072,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
}
- if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
- !force_hs_execp) {
+ if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)) {
/* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
@@ -1116,7 +1094,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
htval = env->guest_phys_fault_addr;
riscv_cpu_set_virt_enabled(env, 0);
- riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
env->hstatus = set_field(env->hstatus, HSTATUS_SPV, false);
@@ -1152,7 +1129,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
/* Trapping to M mode, virt is disabled */
riscv_cpu_set_virt_enabled(env, 0);
- riscv_cpu_set_force_hs_excep(env, 0);
}
s = env->mstatus;
--
2.31.1
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, (continued)
- [PULL v2 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/29
- [PULL v2 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/29
- [PULL v2 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/29
- [PULL v2 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/29
- [PULL v2 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/29
- [PULL v2 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/29
- [PULL v2 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/29
- [PULL v2 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/29
- [PULL v2 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/29
- [PULL v2 15/18] target/riscv: fix VS interrupts forwarding to HS, Alistair Francis, 2021/10/29
- [PULL v2 16/18] target/riscv: remove force HS exception,
Alistair Francis <=
- [PULL v2 17/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/29
- [PULL v2 18/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/29
- Re: [PULL v2 00/18] riscv-to-apply queue, Richard Henderson, 2021/10/29