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[PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu
From: |
Alistair Francis |
Subject: |
[PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu |
Date: |
Sun, 3 Jul 2022 10:12:23 +1000 |
From: Atish Patra <atish.patra@wdc.com>
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-4-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 4 ++--
target/riscv/csr.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7d6397acdf..252c30a55d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -397,7 +397,7 @@ struct RISCVCPUConfig {
bool ext_zksed;
bool ext_zksh;
bool ext_zkt;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
bool ext_svinval;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 05e6521351..1b57b3c439 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -851,7 +851,7 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- cpu->cfg.ext_counters = true;
+ cpu->cfg.ext_pmu = true;
cpu->cfg.ext_ifencei = true;
cpu->cfg.ext_icsr = true;
cpu->cfg.mmu = true;
@@ -879,7 +879,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 58d07c511f..0ca05c7788 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.ext_pmu) {
+ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.36.1
- [PULL v2 00/19] riscv-to-apply queue, Alistair Francis, 2022/07/02
- [PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui, Alistair Francis, 2022/07/02
- [PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal, Alistair Francis, 2022/07/02
- [PULL v2 03/19] target/riscv: Remove generate_exception_mtval, Alistair Francis, 2022/07/02
- [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, Alistair Francis, 2022/07/02
- [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function, Alistair Francis, 2022/07/02
- [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode, Alistair Francis, 2022/07/02
- [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu,
Alistair Francis <=
- [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc, Alistair Francis, 2022/07/02
- [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable, Alistair Francis, 2022/07/02
- [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR, Alistair Francis, 2022/07/02
- [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents, Alistair Francis, 2022/07/02
- [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation, Alistair Francis, 2022/07/02
- [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check, Alistair Francis, 2022/07/02
- [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11, Alistair Francis, 2022/07/02
- [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest, Alistair Francis, 2022/07/02
- [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints, Alistair Francis, 2022/07/02
- [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit, Alistair Francis, 2022/07/02