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[PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check
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From: |
Alistair Francis |
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Subject: |
[PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check |
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Date: |
Sun, 3 Jul 2022 10:12:28 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the
CSR ops.")
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220629233102.275181-2-alistair.francis@opensource.wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d65318dcc6..d14a0cb0a0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3812,7 +3812,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Physical Memory Protection */
[CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
- .min_priv_ver = PRIV_VERSION_1_12_0 },
+ .min_priv_ver = PRIV_VERSION_1_11_0 },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
--
2.36.1
- [PULL v2 03/19] target/riscv: Remove generate_exception_mtval, (continued)
- [PULL v2 03/19] target/riscv: Remove generate_exception_mtval, Alistair Francis, 2022/07/02
- [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, Alistair Francis, 2022/07/02
- [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function, Alistair Francis, 2022/07/02
- [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode, Alistair Francis, 2022/07/02
- [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu, Alistair Francis, 2022/07/02
- [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc, Alistair Francis, 2022/07/02
- [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable, Alistair Francis, 2022/07/02
- [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR, Alistair Francis, 2022/07/02
- [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents, Alistair Francis, 2022/07/02
- [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation, Alistair Francis, 2022/07/02
- [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check,
Alistair Francis <=
- [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11, Alistair Francis, 2022/07/02
- [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest, Alistair Francis, 2022/07/02
- [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints, Alistair Francis, 2022/07/02
- [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit, Alistair Francis, 2022/07/02
- [PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits, Alistair Francis, 2022/07/02
- [PULL v2 19/19] target/riscv: Update default priority table for local interrupts, Alistair Francis, 2022/07/02
- Re: [PULL v2 00/19] riscv-to-apply queue, Richard Henderson, 2022/07/03