[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 10/19] target/riscv: Implement mcountinhibit CSR
From: |
Alistair Francis |
Subject: |
[PULL v2 10/19] target/riscv: Implement mcountinhibit CSR |
Date: |
Sun, 3 Jul 2022 10:12:25 +1000 |
From: Atish Patra <atish.patra@wdc.com>
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220620231603.2547260-6-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 4 ++++
target/riscv/csr.c | 25 +++++++++++++++++++++++++
target/riscv/machine.c | 1 +
4 files changed, 32 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ffee54ea5c..0a916db9f6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -275,6 +275,8 @@ struct CPUArchState {
target_ulong scounteren;
target_ulong mcounteren;
+ target_ulong mcountinhibit;
+
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4d04b20d06..b3f7fa7130 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -367,6 +367,10 @@
#define CSR_MHPMCOUNTER29 0xb1d
#define CSR_MHPMCOUNTER30 0xb1e
#define CSR_MHPMCOUNTER31 0xb1f
+
+/* Machine counter-inhibit register */
+#define CSR_MCOUNTINHIBIT 0x320
+
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b4a8e15f49..94d39a4ce1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1475,6 +1475,28 @@ static RISCVException write_mtvec(CPURISCVState *env,
int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ *val = env->mcountinhibit;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ env->mcountinhibit = val;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3745,6 +3767,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
[CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
+ write_mcountinhibit },
+
[CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
[CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
[CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 2a437b29a1..87cd55bfd3 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -330,6 +330,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
--
2.36.1
- [PULL v2 00/19] riscv-to-apply queue, Alistair Francis, 2022/07/02
- [PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui, Alistair Francis, 2022/07/02
- [PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal, Alistair Francis, 2022/07/02
- [PULL v2 03/19] target/riscv: Remove generate_exception_mtval, Alistair Francis, 2022/07/02
- [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, Alistair Francis, 2022/07/02
- [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function, Alistair Francis, 2022/07/02
- [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode, Alistair Francis, 2022/07/02
- [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu, Alistair Francis, 2022/07/02
- [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc, Alistair Francis, 2022/07/02
- [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable, Alistair Francis, 2022/07/02
- [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR,
Alistair Francis <=
- [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents, Alistair Francis, 2022/07/02
- [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation, Alistair Francis, 2022/07/02
- [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check, Alistair Francis, 2022/07/02
- [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11, Alistair Francis, 2022/07/02
- [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest, Alistair Francis, 2022/07/02
- [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints, Alistair Francis, 2022/07/02
- [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit, Alistair Francis, 2022/07/02
- [PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits, Alistair Francis, 2022/07/02
- [PULL v2 19/19] target/riscv: Update default priority table for local interrupts, Alistair Francis, 2022/07/02
- Re: [PULL v2 00/19] riscv-to-apply queue, Richard Henderson, 2022/07/03