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[PATCH 05/11] hw/i386/pc: QOM'ify RTC creation
From: |
Bernhard Beschow |
Subject: |
[PATCH 05/11] hw/i386/pc: QOM'ify RTC creation |
Date: |
Wed, 13 Jul 2022 10:17:29 +0200 |
Just like in the real hardware, create the RTC in the southbridges.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/i386/pc.c | 12 ++++++++++--
hw/i386/pc_piix.c | 8 ++++++++
hw/i386/pc_q35.c | 1 +
hw/isa/lpc_ich9.c | 8 ++++++++
hw/isa/piix3.c | 7 +++++++
include/hw/i386/ich9.h | 2 ++
include/hw/southbridge/piix.h | 2 ++
7 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index c3602d166d..eba1c98b5a 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1181,9 +1181,17 @@ void pc_basic_device_init(struct PCMachineState *pcms,
pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
}
- *rtc_state = mc146818_rtc_init(isa_bus, 2000, rtc_irq);
- qemu_register_boot_set(pc_boot_set, *rtc_state);
+ if (rtc_irq) {
+ qdev_connect_gpio_out(DEVICE(*rtc_state), 0, rtc_irq);
+ } else {
+ uint32_t irq = object_property_get_uint(OBJECT(*rtc_state),
+ "irq",
+ &error_fatal);
+ isa_connect_gpio_out(*rtc_state, 0, irq);
+ }
+
+ qemu_register_boot_set(pc_boot_set, rtc_state);
if (!xen_enabled() &&
(x86ms->pit == ON_OFF_AUTO_AUTO || x86ms->pit == ON_OFF_AUTO_ON)) {
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 364c73b1bc..52c550f8b8 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -32,6 +32,7 @@
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
#include "hw/pci-host/i440fx.h"
+#include "hw/rtc/mc146818rtc.h"
#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
@@ -224,12 +225,19 @@ static void pc_init1(MachineState *machine,
piix3->pic = x86ms->gsi;
piix3_devfn = piix3->dev.devfn;
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+ rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
+ "rtc"));
piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm");
} else {
pci_bus = NULL;
piix4_pm = NULL;
isa_bus = isa_bus_new(NULL, get_system_memory(), system_io,
&error_abort);
+
+ rtc_state = isa_new(TYPE_MC146818_RTC);
+ qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000);
+ isa_realize_and_unref(rtc_state, isa_bus, &error_fatal);
+
i8257_dma_init(isa_bus, 0);
pcms->hpet_enabled = false;
}
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index f96cbd04e2..d850313180 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -230,6 +230,7 @@ static void pc_q35_init(MachineState *machine)
lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC), true,
TYPE_ICH9_LPC_DEVICE);
+ rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(lpc), "rtc"));
object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
TYPE_HOTPLUG_HANDLER,
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 8694e58b21..0051fa66ab 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -660,6 +660,8 @@ static void ich9_lpc_initfn(Object *obj)
static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+ object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC);
+
object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
&lpc->sci_gsi, OBJ_PROP_FLAG_READ);
object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
@@ -725,6 +727,12 @@ static void ich9_lpc_realize(PCIDevice *d, Error **errp)
isa_bus_irqs(isa_bus, lpc->gsi);
i8257_dma_init(isa_bus, 0);
+
+ /* RTC */
+ qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000);
+ if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) {
+ return;
+ }
}
static bool ich9_rst_cnt_needed(void *opaque)
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 5db0bbf7b6..afd36178dd 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -315,6 +315,12 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
i8257_dma_init(isa_bus, 0);
+ /* RTC */
+ qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
+ if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
+ return;
+ }
+
/* USB */
if (d->has_usb) {
qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
@@ -353,6 +359,7 @@ static void pci_piix3_init(Object *obj)
{
PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+ object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci");
object_initialize_child(obj, "pm", &d->pm, TYPE_PIIX4_PM);
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 23ee8e371b..672efc6bce 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -11,6 +11,7 @@
#include "hw/acpi/acpi.h"
#include "hw/acpi/ich9.h"
#include "hw/pci/pci_bus.h"
+#include "hw/rtc/mc146818rtc.h"
#include "qom/object.h"
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
@@ -39,6 +40,7 @@ struct ICH9LPCState {
*/
uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+ RTCState rtc;
APMState apm;
ICH9LPCPMRegs pm;
uint32_t sci_level; /* track sci level */
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index ee847cb4f2..15b05cfc93 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -15,6 +15,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
#include "hw/acpi/piix4.h"
+#include "hw/rtc/mc146818rtc.h"
#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
@@ -54,6 +55,7 @@ struct PIIXState {
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+ RTCState rtc;
UHCIState uhci;
PIIX4PMState pm;
--
2.37.1
- [PATCH 00/11] QOM'ify PIIX3 southbridge, Bernhard Beschow, 2022/07/13
- [PATCH 01/11] hw/i386/pc: QOM'ify DMA creation, Bernhard Beschow, 2022/07/13
- [PATCH 04/11] hw/isa/piix3: QOM'ify ACPI controller creation, Bernhard Beschow, 2022/07/13
- [PATCH 06/11] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2022/07/13
- [PATCH 09/11] hw/isa/piix3: QOM'ify IDE controller creation, Bernhard Beschow, 2022/07/13
- [PATCH 05/11] hw/i386/pc: QOM'ify RTC creation,
Bernhard Beschow <=
- [PATCH 08/11] hw/isa/piix3: QOM'ify ISA PIC creation, Bernhard Beschow, 2022/07/13
- [PATCH 07/11] hw/intc/i8259: Introduce i8259 proxy "isa-pic", Bernhard Beschow, 2022/07/13
- [PATCH 11/11] hw/isa/piix3: Remove extra ';' outside of functions, Bernhard Beschow, 2022/07/13
- [PATCH 02/11] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 southbridge, Bernhard Beschow, 2022/07/13
- [PATCH 03/11] hw/isa/piix3: QOM'ify USB controller creation, Bernhard Beschow, 2022/07/13
- [PATCH 10/11] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/07/13
- Re: [PATCH 00/11] QOM'ify PIIX3 southbridge, Michael S. Tsirkin, 2022/07/26