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[PATCH 03/11] hw/isa/piix3: QOM'ify USB controller creation
From: |
Bernhard Beschow |
Subject: |
[PATCH 03/11] hw/isa/piix3: QOM'ify USB controller creation |
Date: |
Wed, 13 Jul 2022 10:17:27 +0200 |
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the southbridge.
Note that the USB function is optional in QEMU. This is why it gets
unparented if it is disabled, otherwiese QEMU will abort with:
src/hw/core/qdev.c:357: qdev_assert_realized_properly_cb: Assertion
`dev->realized' failed
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/i386/pc_piix.c | 6 ++----
hw/isa/piix3.c | 26 ++++++++++++++++++++++++++
include/hw/southbridge/piix.h | 5 +++++
3 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index f129da29ac..96dc0db729 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -210,6 +210,8 @@ static void pc_init1(MachineState *machine,
pcms->bus = pci_bus;
pci_dev = pci_new_multifunction(-1, true, type);
+ object_property_set_bool(OBJECT(pci_dev), "has-usb",
+ machine_usb(machine), &error_abort);
pci_realize_and_unref(pci_dev, pci_bus, &error_fatal);
piix3 = PIIX3_PCI_DEVICE(pci_dev);
piix3->pic = x86ms->gsi;
@@ -281,10 +283,6 @@ static void pc_init1(MachineState *machine,
}
#endif
- if (pcmc->pci_enabled && machine_usb(machine)) {
- pci_create_simple(pci_bus, piix3_devfn + 2, "piix3-usb-uhci");
- }
-
if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
PCIDevice *piix4_pm;
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
index 44a9998752..dd512cca84 100644
--- a/hw/isa/piix3.c
+++ b/hw/isa/piix3.c
@@ -27,6 +27,7 @@
#include "qapi/error.h"
#include "hw/dma/i8257.h"
#include "hw/southbridge/piix.h"
+#include "hw/ide/pci.h"
#include "hw/irq.h"
#include "hw/isa/isa.h"
#include "hw/xen/xen.h"
@@ -296,6 +297,7 @@ static const MemoryRegionOps rcr_ops = {
static void pci_piix3_realize(PCIDevice *dev, Error **errp)
{
PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+ PCIBus *pci_bus = pci_get_bus(dev);
ISABus *isa_bus;
isa_bus = isa_bus_new(DEVICE(d), get_system_memory(),
@@ -312,6 +314,16 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp)
qemu_register_reset(piix3_reset, d);
i8257_dma_init(isa_bus, 0);
+
+ /* USB */
+ if (d->has_usb) {
+ qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
+ if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
+ return;
+ }
+ } else {
+ object_unparent(OBJECT(&d->uhci));
+ }
}
static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
@@ -327,6 +339,18 @@ static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml
*scope)
}
}
+static void pci_piix3_init(Object *obj)
+{
+ PIIX3State *d = PIIX3_PCI_DEVICE(obj);
+
+ object_initialize_child(obj, "uhci", &d->uhci, "piix3-usb-uhci");
+}
+
+static Property pci_piix3_props[] = {
+ DEFINE_PROP_BOOL("has-usb", PIIX3State, has_usb, true),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void pci_piix3_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -345,12 +369,14 @@ static void pci_piix3_class_init(ObjectClass *klass, void
*data)
* pc_piix.c's pc_init1()
*/
dc->user_creatable = false;
+ device_class_set_props(dc, pci_piix3_props);
adevc->build_dev_aml = build_pci_isa_aml;
}
static const TypeInfo piix3_pci_type_info = {
.name = TYPE_PIIX3_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
+ .instance_init = pci_piix3_init,
.instance_size = sizeof(PIIX3State),
.abstract = true,
.class_init = pci_piix3_class_init,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 2693778b23..115311d932 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -14,6 +14,7 @@
#include "hw/pci/pci.h"
#include "qom/object.h"
+#include "hw/usb/hcd-uhci.h"
/* PIRQRC[A:D]: PIRQx Route Control Registers */
#define PIIX_PIRQCA 0x60
@@ -52,11 +53,15 @@ struct PIIXState {
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+ UHCIState uhci;
+
/* Reset Control Register contents */
uint8_t rcr;
/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
+
+ bool has_usb;
};
typedef struct PIIXState PIIX3State;
--
2.37.1
- [PATCH 06/11] hw/i386/pc: No need for rtc_state to be an out-parameter, (continued)
- [PATCH 06/11] hw/i386/pc: No need for rtc_state to be an out-parameter, Bernhard Beschow, 2022/07/13
- [PATCH 09/11] hw/isa/piix3: QOM'ify IDE controller creation, Bernhard Beschow, 2022/07/13
- [PATCH 05/11] hw/i386/pc: QOM'ify RTC creation, Bernhard Beschow, 2022/07/13
- [PATCH 08/11] hw/isa/piix3: QOM'ify ISA PIC creation, Bernhard Beschow, 2022/07/13
- [PATCH 07/11] hw/intc/i8259: Introduce i8259 proxy "isa-pic", Bernhard Beschow, 2022/07/13
- [PATCH 11/11] hw/isa/piix3: Remove extra ';' outside of functions, Bernhard Beschow, 2022/07/13
- [PATCH 02/11] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 southbridge, Bernhard Beschow, 2022/07/13
- [PATCH 03/11] hw/isa/piix3: QOM'ify USB controller creation,
Bernhard Beschow <=
- [PATCH 10/11] hw/isa/piix3: Wire up ACPI interrupt internally, Bernhard Beschow, 2022/07/13
- Re: [PATCH 00/11] QOM'ify PIIX3 southbridge, Michael S. Tsirkin, 2022/07/26