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[PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32
From: |
Tobias Roehmel |
Subject: |
[PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32 |
Date: |
Mon, 18 Jul 2022 13:54:30 +0200 |
From: Tobias Röhmel <quic_trohmel@quicinc.com>
ARMv8-R AArch32 CPUs behave as if TTBCR.EAE is always 1 even
tough they don't have the TTBCR register.
See ARM Architecture Reference Manual Supplement - ARMv8, for the ARMv8-R
AArch32 architecture profile Version:A.c section C1.2.
Signed-off-by: Tobias Röhmel <quic_trohmel@quicinc.com>
---
target/arm/debug_helper.c | 3 ++-
target/arm/internals.h | 3 ++-
target/arm/tlb_helper.c | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index b18a6bd3a2..44b1e32974 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -434,7 +434,8 @@ static uint32_t arm_debug_exception_fsr(CPUARMState *env)
using_lpae = true;
} else {
if (arm_feature(env, ARM_FEATURE_LPAE) &&
- (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
+ ((env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)
+ || arm_feature(env, ARM_FEATURE_V8_R))) {
using_lpae = true;
}
}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b03049d920..e2a2b03d41 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -254,7 +254,8 @@ static inline bool extended_addresses_enabled(CPUARMState
*env)
{
TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
return arm_el_is_aa64(env, 1) ||
- (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
+ (arm_feature(env, ARM_FEATURE_LPAE) && ((tcr->raw_tcr & TTBCR_EAE)
+ || arm_feature(env, ARM_FEATURE_V8_R)));
}
/* Update a QEMU watchpoint based on the information the guest has set in the
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
index 7d8a86b3c4..891326edb8 100644
--- a/target/arm/tlb_helper.c
+++ b/target/arm/tlb_helper.c
@@ -20,7 +20,8 @@ bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx
mmu_idx)
return true;
}
if (arm_feature(env, ARM_FEATURE_LPAE)
- && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
+ && ((regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)
+ || arm_feature(env, ARM_FEATURE_V8_R))) {
return true;
}
return false;
--
2.25.1
- [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/18
- [PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32,
Tobias Roehmel <=
- [PATCH v2 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs, Tobias Roehmel, 2022/07/18
- [PATCH v2 7/9] target/arm: Add PMSAv8r registers, Tobias Roehmel, 2022/07/18
- [PATCH v2 9/9] target/arm: Add ARM Cortex-R52 cpu, Tobias Roehmel, 2022/07/18
- [PATCH v2 1/9] target/arm: Add ARM_FEATURE_V8_R, Tobias Roehmel, 2022/07/18
- [PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R, Tobias Roehmel, 2022/07/18
- [PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional, Tobias Roehmel, 2022/07/18
- [PATCH v2 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup, Tobias Roehmel, 2022/07/18
- [PATCH v2 8/9] target/arm: Add PMSAv8r functionality, Tobias Roehmel, 2022/07/18
- Re: [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/27