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[PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R
From: |
Tobias Roehmel |
Subject: |
[PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R |
Date: |
Mon, 18 Jul 2022 13:54:26 +0200 |
From: Tobias Röhmel <quic_trohmel@quicinc.com>
Cortex-R52 has the MPUIR register which has the same encoding
has the MIDR alias with opc2=4. So we only add that alias
when we are not realizing a Cortex-R.
Signed-off-by: Tobias Röhmel <quic_trohmel@quicinc.com>
---
target/arm/helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6457e6301c..03bdc3d149 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8189,9 +8189,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.readfn = midr_read },
/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
- { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
- .access = PL1_R, .resetvalue = cpu->midr },
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
.access = PL1_R, .resetvalue = cpu->midr },
@@ -8201,6 +8198,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa64_tid1,
.type = ARM_CP_CONST, .resetvalue = cpu->revidr },
};
+ ARMCPRegInfo id_v8_midr_alias_cp_reginfo[] = {
+ { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
+ .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
+ .access = PL1_R, .resetvalue = cpu->midr },
+ };
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
{ .name = "CTR",
@@ -8264,8 +8266,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
id_mpuir_reginfo.access = PL1_RW;
id_tlbtr_reginfo.access = PL1_RW;
}
+
if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
+ if (!arm_feature(env, ARM_FEATURE_V8_R)) {
+ define_arm_cp_regs(cpu, id_v8_midr_alias_cp_reginfo);
+ }
} else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
}
--
2.25.1
- [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/18
- [PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, Tobias Roehmel, 2022/07/18
- [PATCH v2 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs, Tobias Roehmel, 2022/07/18
- [PATCH v2 7/9] target/arm: Add PMSAv8r registers, Tobias Roehmel, 2022/07/18
- [PATCH v2 9/9] target/arm: Add ARM Cortex-R52 cpu, Tobias Roehmel, 2022/07/18
- [PATCH v2 1/9] target/arm: Add ARM_FEATURE_V8_R, Tobias Roehmel, 2022/07/18
- [PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R,
Tobias Roehmel <=
- [PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional, Tobias Roehmel, 2022/07/18
- [PATCH v2 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup, Tobias Roehmel, 2022/07/18
- [PATCH v2 8/9] target/arm: Add PMSAv8r functionality, Tobias Roehmel, 2022/07/18
- Re: [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/27