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[PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes opti
From: |
Tobias Roehmel |
Subject: |
[PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional |
Date: |
Mon, 18 Jul 2022 13:54:28 +0200 |
From: Tobias Röhmel <quic_trohmel@quicinc.com>
The Cortex-R52 has a 2 stage MPU translation process but doesn't have the
FEAT_S2FWB feature. This makes it neccessary to allow for the old cache
attribut combination.
This is facilitated by changing the control path of combine_cacheattrs instead
of failing if the second cache attributes struct is not in that format.
Signed-off-by: Tobias Röhmel <quic_trohmel@quicinc.com>
---
target/arm/ptw.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 4d97a24808..8b037c1f55 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2108,7 +2108,11 @@ static uint8_t combined_attrs_nofwb(CPUARMState *env,
{
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
- s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
+ if (s2.is_s2_format) {
+ s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
+ } else {
+ s2_mair_attrs = s2.attrs;
+ }
s1lo = extract32(s1.attrs, 0, 4);
s2lo = extract32(s2_mair_attrs, 0, 4);
@@ -2166,6 +2170,8 @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
static uint8_t combined_attrs_fwb(CPUARMState *env,
ARMCacheAttrs s1, ARMCacheAttrs s2)
{
+ assert(s2.is_s2_format && !s1.is_s2_format);
+
switch (s2.attrs) {
case 7:
/* Use stage 1 attributes */
@@ -2215,7 +2221,6 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
ARMCacheAttrs ret;
bool tagged = false;
- assert(s2.is_s2_format && !s1.is_s2_format);
ret.is_s2_format = false;
if (s1.attrs == 0xf0) {
--
2.25.1
- [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/18
- [PATCH v2 6/9] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, Tobias Roehmel, 2022/07/18
- [PATCH v2 3/9] target/arm: Make RVBAR available for all ARMv8 CPUs, Tobias Roehmel, 2022/07/18
- [PATCH v2 7/9] target/arm: Add PMSAv8r registers, Tobias Roehmel, 2022/07/18
- [PATCH v2 9/9] target/arm: Add ARM Cortex-R52 cpu, Tobias Roehmel, 2022/07/18
- [PATCH v2 1/9] target/arm: Add ARM_FEATURE_V8_R, Tobias Roehmel, 2022/07/18
- [PATCH v2 2/9] target/arm: Don't add all MIDR aliases for Cortex-R, Tobias Roehmel, 2022/07/18
- [PATCH v2 4/9] target/arm: Make stage_2_format for cache attributes optional,
Tobias Roehmel <=
- [PATCH v2 5/9] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup, Tobias Roehmel, 2022/07/18
- [PATCH v2 8/9] target/arm: Add PMSAv8r functionality, Tobias Roehmel, 2022/07/18
- Re: [PATCH v2 0/9] Add Cortex-R52, Tobias Roehmel, 2022/07/27