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[PULL 00/15] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/15] target-arm queue |
Date: |
Mon, 18 Jul 2022 14:59:05 +0100 |
Some arm patches before softfreeze. These are all bug fixes.
-- PMM
The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9:
Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into
staging (2022-07-15 15:38:13 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220718
for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7:
Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:25:13 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
* target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
* target/arm: Fix aarch64_sve_change_el for SME
* linux-user/aarch64: Do not clear PROT_MTE on mprotect
* target/arm: Honour VTCR_EL2 bits in Secure EL2
* hw/adc: Fix CONV bit in NPCM7XX ADC CON register
* hw/adc: Make adci[*] R/W in NPCM7XX ADC
* target/arm: Don't set syndrome ISS for loads and stores with writeback
* Align Raspberry Pi DMA interrupts with Linux DTS
----------------------------------------------------------------
Andrey Makarov (1):
Align Raspberry Pi DMA interrupts with Linux DTS
Hao Wu (2):
hw/adc: Fix CONV bit in NPCM7XX ADC CON register
hw/adc: Make adci[*] R/W in NPCM7XX ADC
Peter Maydell (9):
hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
target/arm: Define and use new regime_tcr_value() function
target/arm: Calculate mask/base_mask in get_level1_table_address()
target/arm: Fold regime_tcr() and regime_tcr_value() together
target/arm: Fix big-endian host handling of VTCR
target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t
target/arm: Store TCR_EL* registers as uint64_t
target/arm: Honour VTCR_EL2 bits in Secure EL2
target/arm: Don't set syndrome ISS for loads and stores with writeback
Richard Henderson (3):
target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
target/arm: Fix aarch64_sve_change_el for SME
linux-user/aarch64: Do not clear PROT_MTE on mprotect
include/hw/arm/bcm2835_peripherals.h | 2 +
target/arm/cpu.h | 38 ++++++++---
target/arm/internals.h | 34 +++++++---
accel/tcg/translate-all.c | 13 +++-
hw/adc/npcm7xx_adc.c | 4 +-
hw/arm/bcm2835_peripherals.c | 26 ++++++-
hw/intc/armv7m_nvic.c | 9 ++-
target/arm/cpu.c | 2 +-
target/arm/debug_helper.c | 2 +-
target/arm/helper.c | 128 ++++++++++++++++-------------------
target/arm/ptw.c | 38 ++++++-----
target/arm/tlb_helper.c | 2 +-
target/arm/translate-a64.c | 4 +-
tests/qtest/bcm2835-dma-test.c | 118 ++++++++++++++++++++++++++++++++
tests/qtest/npcm7xx_adc-test.c | 2 +-
tests/qtest/meson.build | 3 +-
16 files changed, 306 insertions(+), 119 deletions(-)
create mode 100644 tests/qtest/bcm2835-dma-test.c
- [PULL 00/15] target-arm queue,
Peter Maydell <=
- [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high, Peter Maydell, 2022/07/18
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME, Peter Maydell, 2022/07/18
- [PULL 05/15] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/18
- [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register, Peter Maydell, 2022/07/18
- [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect, Peter Maydell, 2022/07/18
- [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled, Peter Maydell, 2022/07/18
- [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 08/15] target/arm: Fix big-endian host handling of VTCR, Peter Maydell, 2022/07/18
- [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address(), Peter Maydell, 2022/07/18