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[PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register
From: |
Peter Maydell |
Subject: |
[PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register |
Date: |
Mon, 18 Jul 2022 14:59:17 +0100 |
From: Hao Wu <wuhaotsh@google.com>
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture<venture@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220714182836.89602-4-wuhaotsh@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/adc/npcm7xx_adc.c | 2 +-
tests/qtest/npcm7xx_adc-test.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
index 0f0a9f63e20..47fb9e5f74c 100644
--- a/hw/adc/npcm7xx_adc.c
+++ b/hw/adc/npcm7xx_adc.c
@@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4)
#define NPCM7XX_ADC_CON_INT BIT(18)
#define NPCM7XX_ADC_CON_EN BIT(17)
#define NPCM7XX_ADC_CON_RST BIT(16)
-#define NPCM7XX_ADC_CON_CONV BIT(14)
+#define NPCM7XX_ADC_CON_CONV BIT(13)
#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
#define NPCM7XX_ADC_MAX_RESULT 1023
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
index 3fa6d9ece0b..8048044d281 100644
--- a/tests/qtest/npcm7xx_adc-test.c
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -50,7 +50,7 @@
#define CON_INT BIT(18)
#define CON_EN BIT(17)
#define CON_RST BIT(16)
-#define CON_CONV BIT(14)
+#define CON_CONV BIT(13)
#define CON_DIV(rv) extract32(rv, 1, 8)
#define FST_RDST BIT(1)
--
2.25.1
- [PULL 00/15] target-arm queue, Peter Maydell, 2022/07/18
- [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high, Peter Maydell, 2022/07/18
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME, Peter Maydell, 2022/07/18
- [PULL 05/15] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/18
- [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register,
Peter Maydell <=
- [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect, Peter Maydell, 2022/07/18
- [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled, Peter Maydell, 2022/07/18
- [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 08/15] target/arm: Fix big-endian host handling of VTCR, Peter Maydell, 2022/07/18
- [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address(), Peter Maydell, 2022/07/18
- [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2, Peter Maydell, 2022/07/18
- [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback, Peter Maydell, 2022/07/18
- [PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC, Peter Maydell, 2022/07/18
- [PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS, Peter Maydell, 2022/07/18
- [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together, Peter Maydell, 2022/07/18