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[PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores wit
From: |
Peter Maydell |
Subject: |
[PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback |
Date: |
Mon, 18 Jul 2022 14:59:19 +0100 |
The architecture requires that for faults on loads and stores which
do writeback, the syndrome information does not have the ISS
instruction syndrome information (i.e. ISV is 0). We got this wrong
for the load and store instructions covered by disas_ldst_reg_imm9().
Calculate iss_valid correctly so that if the insn is a writeback one
it is false.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org
---
target/arm/translate-a64.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b7b64f73584..163df8c6157 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3138,7 +3138,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn,
bool is_store = false;
bool is_extended = false;
bool is_unpriv = (idx == 2);
- bool iss_valid = !is_vector;
+ bool iss_valid;
bool post_index;
bool writeback;
int memidx;
@@ -3191,6 +3191,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t
insn,
g_assert_not_reached();
}
+ iss_valid = !is_vector && !writeback;
+
if (rn == 31) {
gen_check_sp_alignment(s);
}
--
2.25.1
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME, (continued)
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME, Peter Maydell, 2022/07/18
- [PULL 05/15] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/18
- [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register, Peter Maydell, 2022/07/18
- [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect, Peter Maydell, 2022/07/18
- [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled, Peter Maydell, 2022/07/18
- [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 08/15] target/arm: Fix big-endian host handling of VTCR, Peter Maydell, 2022/07/18
- [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address(), Peter Maydell, 2022/07/18
- [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2, Peter Maydell, 2022/07/18
- [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback,
Peter Maydell <=
- [PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC, Peter Maydell, 2022/07/18
- [PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS, Peter Maydell, 2022/07/18
- [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together, Peter Maydell, 2022/07/18
- Re: [PULL 00/15] target-arm queue, Peter Maydell, 2022/07/18