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[PULL 08/15] target/arm: Fix big-endian host handling of VTCR
From: |
Peter Maydell |
Subject: |
[PULL 08/15] target/arm: Fix big-endian host handling of VTCR |
Date: |
Mon, 18 Jul 2022 14:59:13 +0100 |
We have a bug in our handling of accesses to the AArch32 VTCR
register on big-endian hosts: we were not adjusting the part of the
uint64_t field within TCR that the generated code would access. That
can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg
struct, or by defining a full set of read/write/reset functions --
the various other TCR cpreg structs used one or another of those
strategies, but for VTCR we did not, so on a big-endian host VTCR
accesses would touch the wrong half of the register.
Use offsetoflow32() in the VTCR register struct. This works even
though the field in the CPU struct is currently a struct TCR, because
the first field in that struct is the uint64_t raw_tcr.
None of the other TCR registers have this bug -- either they are
AArch64 only, or else they define resetfn, writefn, etc, and
expect to be passed the full struct pointer.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220714132303.1287193-5-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8847f5b90ad..7461d4091ef 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5409,7 +5409,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
.type = ARM_CP_ALIAS,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
- .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vtcr_el2) },
{ .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
.access = PL2_RW,
--
2.25.1
- [PULL 00/15] target-arm queue, Peter Maydell, 2022/07/18
- [PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high, Peter Maydell, 2022/07/18
- [PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME, Peter Maydell, 2022/07/18
- [PULL 05/15] target/arm: Define and use new regime_tcr_value() function, Peter Maydell, 2022/07/18
- [PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register, Peter Maydell, 2022/07/18
- [PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect, Peter Maydell, 2022/07/18
- [PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled, Peter Maydell, 2022/07/18
- [PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t, Peter Maydell, 2022/07/18
- [PULL 08/15] target/arm: Fix big-endian host handling of VTCR,
Peter Maydell <=
- [PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address(), Peter Maydell, 2022/07/18
- [PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2, Peter Maydell, 2022/07/18
- [PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback, Peter Maydell, 2022/07/18
- [PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC, Peter Maydell, 2022/07/18
- [PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS, Peter Maydell, 2022/07/18
- [PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together, Peter Maydell, 2022/07/18
- Re: [PULL 00/15] target-arm queue, Peter Maydell, 2022/07/18