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[PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region
From: |
Richard Henderson |
Subject: |
[PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region |
Date: |
Mon, 5 Jun 2023 13:15:21 -0700 |
Fixes an assert in tcg_gen_code that we don't accidentally
eliminate an insn_start during optimization.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 9d2c7a3337..76f46d268b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2146,9 +2146,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State
*env)
/* The entire region has been translated. */
ctx->envflags &= ~TB_FLAG_GUSA_MASK;
- ctx->base.pc_next = pc_end;
- ctx->base.num_insns += max_insns - 1;
- return;
+ goto done;
fail:
qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n",
@@ -2165,8 +2163,19 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State
*env)
purposes of accounting within the TB. We might as well report the
entire region consumed via ctx->base.pc_next so that it's immediately
available in the disassembly dump. */
+
+ done:
ctx->base.pc_next = pc_end;
ctx->base.num_insns += max_insns - 1;
+
+ /*
+ * Emit insn_start to cover each of the insns in the region.
+ * This matches an assert in tcg.c making sure that we have
+ * tb->icount * insn_start.
+ */
+ for (i = 1; i < max_insns; ++i) {
+ tcg_gen_insn_start(pc + i * 2, ctx->envflags);
+ }
}
#endif
--
2.34.1
- [PULL 13/52] tcg: Split out tcg/oversized-guest.h, (continued)
- [PULL 13/52] tcg: Split out tcg/oversized-guest.h, Richard Henderson, 2023/06/05
- [PULL 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL, Richard Henderson, 2023/06/05
- [PULL 10/52] *: Add missing includes of tcg/tcg.h, Richard Henderson, 2023/06/05
- [PULL 12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST, Richard Henderson, 2023/06/05
- [PULL 14/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h, Richard Henderson, 2023/06/05
- [PULL 18/52] tcg: Remove outdated comments in helper-head.h, Richard Henderson, 2023/06/05
- [PULL 17/52] target/hexagon: Include helper-gen.h where needed, Richard Henderson, 2023/06/05
- [PULL 16/52] target/arm: Include helper-gen.h in translator.h, Richard Henderson, 2023/06/05
- [PULL 19/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h, Richard Henderson, 2023/06/05
- [PULL 21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line, Richard Henderson, 2023/06/05
- [PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region,
Richard Henderson <=
- [PULL 26/52] tcg: Add insn_start_words to TCGContext, Richard Henderson, 2023/06/05
- [PULL 27/52] tcg: Add guest_mo to TCGContext, Richard Henderson, 2023/06/05
- [PULL 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits, Richard Henderson, 2023/06/05
- [PULL 24/52] tcg: Split helper-proto.h, Richard Henderson, 2023/06/05
- [PULL 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits, Richard Henderson, 2023/06/05
- [PULL 29/52] tcg: Split tcg/tcg-op-gvec.h, Richard Henderson, 2023/06/05
- [PULL 35/52] accel/tcg: Move most of gen-icount.h into translator.c, Richard Henderson, 2023/06/05
- [PULL 33/52] tcg: Spit out exec/translation-block.h, Richard Henderson, 2023/06/05
- [PULL 31/52] exec-all: Widen tb_page_addr_t for user-only, Richard Henderson, 2023/06/05
- [PULL 30/52] tcg: Remove NO_CPU_IO_DEFS, Richard Henderson, 2023/06/05