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[PULL 28/42] target/arm: Load/store integer pair with one tcg operation
From: |
Peter Maydell |
Subject: |
[PULL 28/42] target/arm: Load/store integer pair with one tcg operation |
Date: |
Tue, 6 Jun 2023 10:48:00 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This is required for LSE2, where the pair must be treated atomically if
it does not cross a 16-byte boundary. But it simplifies the code to do
this always.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 70 ++++++++++++++++++++++++++--------
1 file changed, 55 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 729947b11a4..88183f9dca1 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -2942,26 +2942,66 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
} else {
TCGv_i64 tcg_rt = cpu_reg(s, rt);
TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
+ MemOp mop = size + 1;
+
+ /*
+ * With LSE2, non-sign-extending pairs are treated atomically if
+ * aligned, and if unaligned one of the pair will be completely
+ * within a 16-byte block and that element will be atomic.
+ * Otherwise each element is separately atomic.
+ * In all cases, issue one operation with the correct atomicity.
+ *
+ * This treats sign-extending loads like zero-extending loads,
+ * since that reuses the most code below.
+ */
+ if (s->align_mem) {
+ mop |= (size == 2 ? MO_ALIGN_4 : MO_ALIGN_8);
+ }
+ mop = finalize_memop_pair(s, mop);
if (is_load) {
- TCGv_i64 tmp = tcg_temp_new_i64();
+ if (size == 2) {
+ int o2 = s->be_data == MO_LE ? 32 : 0;
+ int o1 = o2 ^ 32;
- /* Do not modify tcg_rt before recognizing any exception
- * from the second load.
- */
- do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN,
- false, false, 0, false, false);
- tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
- do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN,
- false, false, 0, false, false);
+ tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop);
+ if (is_signed) {
+ tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32);
+ tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32);
+ } else {
+ tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32);
+ tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32);
+ }
+ } else {
+ TCGv_i128 tmp = tcg_temp_new_i128();
- tcg_gen_mov_i64(tcg_rt, tmp);
+ tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop);
+ if (s->be_data == MO_LE) {
+ tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp);
+ } else {
+ tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp);
+ }
+ }
} else {
- do_gpr_st(s, tcg_rt, clean_addr, size,
- false, 0, false, false);
- tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
- do_gpr_st(s, tcg_rt2, clean_addr, size,
- false, 0, false, false);
+ if (size == 2) {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ if (s->be_data == MO_LE) {
+ tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2);
+ } else {
+ tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt);
+ }
+ tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop);
+ } else {
+ TCGv_i128 tmp = tcg_temp_new_i128();
+
+ if (s->be_data == MO_LE) {
+ tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2);
+ } else {
+ tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt);
+ }
+ tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop);
+ }
}
}
--
2.34.1
- [PULL 00/42] target-arm queue, Peter Maydell, 2023/06/06
- [PULL 02/42] hvf: handle access for more registers, Peter Maydell, 2023/06/06
- [PULL 01/42] arm: move KVM breakpoints helpers, Peter Maydell, 2023/06/06
- [PULL 04/42] hvf: add guest debugging handlers for Apple Silicon hosts, Peter Maydell, 2023/06/06
- [PULL 06/42] xlnx-versal: Connect Xilinx VERSAL CANFD controllers, Peter Maydell, 2023/06/06
- [PULL 12/42] hw: arm: allwinner-r40: Add i2c0 device, Peter Maydell, 2023/06/06
- [PULL 15/42] hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support, Peter Maydell, 2023/06/06
- [PULL 14/42] hw/arm/allwinner-r40: add SDRAM controller device, Peter Maydell, 2023/06/06
- [PULL 09/42] hw: arm: Add bananapi M2-Ultra and allwinner-r40 support, Peter Maydell, 2023/06/06
- [PULL 19/42] docs: system: arm: Introduce bananapi_m2u, Peter Maydell, 2023/06/06
- [PULL 28/42] target/arm: Load/store integer pair with one tcg operation,
Peter Maydell <=
- [PULL 03/42] hvf: add breakpoint handlers, Peter Maydell, 2023/06/06
- [PULL 08/42] tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller, Peter Maydell, 2023/06/06
- [PULL 13/42] hw/misc: Rename axp209 to axp22x and add support AXP221 PMU, Peter Maydell, 2023/06/06
- [PULL 17/42] hw: arm: allwinner-sramc: Add SRAM Controller support for R40, Peter Maydell, 2023/06/06
- [PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}, Peter Maydell, 2023/06/06
- [PULL 32/42] target/arm: Pass single_memop to gen_mte_checkN, Peter Maydell, 2023/06/06
- [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN, Peter Maydell, 2023/06/06
- [PULL 16/42] hw: arm: allwinner-r40: Add emac and gmac support, Peter Maydell, 2023/06/06
- [PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair}, Peter Maydell, 2023/06/06
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, Peter Maydell, 2023/06/06