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[PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair}
From: |
Peter Maydell |
Subject: |
[PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair} |
Date: |
Tue, 6 Jun 2023 10:47:54 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Let finalize_memop_atom be the new basic function, with
finalize_memop and finalize_memop_pair testing FEAT_LSE2
to apply the appropriate atomicity.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate.h | 39 +++++++++++++++++++++++++++++-----
target/arm/tcg/translate-a64.c | 2 ++
target/arm/tcg/translate.c | 1 +
3 files changed, 37 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 4d88197715b..c1e57a52ca2 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -90,6 +90,7 @@ typedef struct DisasContext {
uint64_t features; /* CPU features bits */
bool aarch64;
bool thumb;
+ bool lse2;
/* Because unallocated encodings generate different exception syndrome
* information from traps due to FP being disabled, we can't do a single
* "is fp access disabled" check at a high level in the decode tree.
@@ -557,12 +558,13 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
}
/**
- * finalize_memop:
+ * finalize_memop_atom:
* @s: DisasContext
* @opc: size+sign+align of the memory operation
+ * @atom: atomicity of the memory operation
*
- * Build the complete MemOp for a memory operation, including alignment
- * and endianness.
+ * Build the complete MemOp for a memory operation, including alignment,
+ * endianness, and atomicity.
*
* If (op & MO_AMASK) then the operation already contains the required
* alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
@@ -572,12 +574,39 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour
flavour)
* and this is applied here. Note that there is no way to indicate that
* no alignment should ever be enforced; this must be handled manually.
*/
-static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom)
{
if (s->align_mem && !(opc & MO_AMASK)) {
opc |= MO_ALIGN;
}
- return opc | s->be_data;
+ return opc | atom | s->be_data;
+}
+
+/**
+ * finalize_memop:
+ * @s: DisasContext
+ * @opc: size+sign+align of the memory operation
+ *
+ * Like finalize_memop_atom, but with default atomicity.
+ */
+static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+{
+ MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;
+ return finalize_memop_atom(s, opc, atom);
+}
+
+/**
+ * finalize_memop_pair:
+ * @s: DisasContext
+ * @opc: size+sign+align of the memory operation
+ *
+ * Like finalize_memop_atom, but with atomicity for a pair.
+ * C.f. Pseudocode for Mem[], operand ispair.
+ */
+static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc)
+{
+ MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;
+ return finalize_memop_atom(s, opc, atom);
}
/**
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index d9800337cf4..1d34c5a7031 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -14098,6 +14098,8 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
tcg_debug_assert(dc->tbid & 1);
#endif
+ dc->lse2 = dc_isar_feature(aa64_lse2, dc);
+
/* Single step state. The code-generation logic here is:
* SS_ACTIVE == 0:
* generate code with no special handling for single-stepping (except
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index a68d3c7f6da..13c88ba1b9f 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -9168,6 +9168,7 @@ static void arm_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
dc->sme_trap_nonstreaming =
EX_TBFLAG_A32(tb_flags, SME_TRAP_NONSTREAMING);
}
+ dc->lse2 = false; /* applies only to aarch64 */
dc->cp_regs = cpu->cp_regs;
dc->features = env->features;
--
2.34.1
- [PULL 19/42] docs: system: arm: Introduce bananapi_m2u, (continued)
- [PULL 19/42] docs: system: arm: Introduce bananapi_m2u, Peter Maydell, 2023/06/06
- [PULL 28/42] target/arm: Load/store integer pair with one tcg operation, Peter Maydell, 2023/06/06
- [PULL 03/42] hvf: add breakpoint handlers, Peter Maydell, 2023/06/06
- [PULL 08/42] tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller, Peter Maydell, 2023/06/06
- [PULL 13/42] hw/misc: Rename axp209 to axp22x and add support AXP221 PMU, Peter Maydell, 2023/06/06
- [PULL 17/42] hw: arm: allwinner-sramc: Add SRAM Controller support for R40, Peter Maydell, 2023/06/06
- [PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}, Peter Maydell, 2023/06/06
- [PULL 32/42] target/arm: Pass single_memop to gen_mte_checkN, Peter Maydell, 2023/06/06
- [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN, Peter Maydell, 2023/06/06
- [PULL 16/42] hw: arm: allwinner-r40: Add emac and gmac support, Peter Maydell, 2023/06/06
- [PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair},
Peter Maydell <=
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, Peter Maydell, 2023/06/06
- [PULL 34/42] target/arm: Add SCTLR.nAA to TBFLAG_A64, Peter Maydell, 2023/06/06
- [PULL 35/42] target/arm: Relax ordered/atomic alignment checks for LSE2, Peter Maydell, 2023/06/06
- [PULL 39/42] target/arm: Enable FEAT_LSE2 for -cpu max, Peter Maydell, 2023/06/06
- [PULL 42/42] target/arm: trap DCC access in user mode emulation, Peter Maydell, 2023/06/06
- [PULL 33/42] target/arm: Check alignment in helper_mte_check, Peter Maydell, 2023/06/06
- [PULL 10/42] hw/arm/allwinner-r40: add Clock Control Unit, Peter Maydell, 2023/06/06
- [PULL 11/42] hw: allwinner-r40: Complete uart devices, Peter Maydell, 2023/06/06
- [PULL 05/42] hw/net/can: Introduce Xilinx Versal CANFD controller, Peter Maydell, 2023/06/06
- [PULL 21/42] target/arm: Add feature test for FEAT_LSE2, Peter Maydell, 2023/06/06