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[PULL 11/42] hw: allwinner-r40: Complete uart devices
From: |
Peter Maydell |
Subject: |
[PULL 11/42] hw: allwinner-r40: Complete uart devices |
Date: |
Tue, 6 Jun 2023 10:47:43 +0100 |
From: qianfan Zhao <qianfanguijin@163.com>
R40 has eight UARTs, support both 16450 and 16550 compatible modes.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/allwinner-r40.h | 8 ++++++++
hw/arm/allwinner-r40.c | 34 +++++++++++++++++++++++++++++++---
2 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
index 3be9dc962be..959b5dc4e04 100644
--- a/include/hw/arm/allwinner-r40.h
+++ b/include/hw/arm/allwinner-r40.h
@@ -41,6 +41,13 @@ enum {
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
AW_R40_DEV_UART0,
+ AW_R40_DEV_UART1,
+ AW_R40_DEV_UART2,
+ AW_R40_DEV_UART3,
+ AW_R40_DEV_UART4,
+ AW_R40_DEV_UART5,
+ AW_R40_DEV_UART6,
+ AW_R40_DEV_UART7,
AW_R40_DEV_GIC_DIST,
AW_R40_DEV_GIC_CPU,
AW_R40_DEV_GIC_HYP,
@@ -70,6 +77,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code.
*/
#define AW_R40_NUM_MMCS 4
+#define AW_R40_NUM_UARTS 8
struct AwR40State {
/*< private >*/
diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c
index 72973f69ff0..537a90b23d8 100644
--- a/hw/arm/allwinner-r40.c
+++ b/hw/arm/allwinner-r40.c
@@ -45,6 +45,13 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00,
[AW_R40_DEV_UART0] = 0x01c28000,
+ [AW_R40_DEV_UART1] = 0x01c28400,
+ [AW_R40_DEV_UART2] = 0x01c28800,
+ [AW_R40_DEV_UART3] = 0x01c28c00,
+ [AW_R40_DEV_UART4] = 0x01c29000,
+ [AW_R40_DEV_UART5] = 0x01c29400,
+ [AW_R40_DEV_UART6] = 0x01c29800,
+ [AW_R40_DEV_UART7] = 0x01c29c00,
[AW_R40_DEV_GIC_DIST] = 0x01c81000,
[AW_R40_DEV_GIC_CPU] = 0x01c82000,
[AW_R40_DEV_GIC_HYP] = 0x01c84000,
@@ -157,6 +164,13 @@ enum {
/* Shared Processor Interrupts */
enum {
AW_R40_GIC_SPI_UART0 = 1,
+ AW_R40_GIC_SPI_UART1 = 2,
+ AW_R40_GIC_SPI_UART2 = 3,
+ AW_R40_GIC_SPI_UART3 = 4,
+ AW_R40_GIC_SPI_UART4 = 17,
+ AW_R40_GIC_SPI_UART5 = 18,
+ AW_R40_GIC_SPI_UART6 = 19,
+ AW_R40_GIC_SPI_UART7 = 20,
AW_R40_GIC_SPI_TIMER0 = 22,
AW_R40_GIC_SPI_TIMER1 = 23,
AW_R40_GIC_SPI_MMC0 = 32,
@@ -384,9 +398,23 @@ static void allwinner_r40_realize(DeviceState *dev, Error
**errp)
}
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
- serial_mm_init(get_system_memory(), s->memmap[AW_R40_DEV_UART0], 2,
- qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_UART0),
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ for (int i = 0; i < AW_R40_NUM_UARTS; i++) {
+ static const int uart_irqs[AW_R40_NUM_UARTS] = {
+ AW_R40_GIC_SPI_UART0,
+ AW_R40_GIC_SPI_UART1,
+ AW_R40_GIC_SPI_UART2,
+ AW_R40_GIC_SPI_UART3,
+ AW_R40_GIC_SPI_UART4,
+ AW_R40_GIC_SPI_UART5,
+ AW_R40_GIC_SPI_UART6,
+ AW_R40_GIC_SPI_UART7,
+ };
+ const hwaddr addr = s->memmap[AW_R40_DEV_UART0 + i];
+
+ serial_mm_init(get_system_memory(), addr, 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
+ 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
+ }
/* Unimplemented devices */
for (i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
--
2.34.1
- [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN, (continued)
- [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN, Peter Maydell, 2023/06/06
- [PULL 16/42] hw: arm: allwinner-r40: Add emac and gmac support, Peter Maydell, 2023/06/06
- [PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair}, Peter Maydell, 2023/06/06
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, Peter Maydell, 2023/06/06
- [PULL 34/42] target/arm: Add SCTLR.nAA to TBFLAG_A64, Peter Maydell, 2023/06/06
- [PULL 35/42] target/arm: Relax ordered/atomic alignment checks for LSE2, Peter Maydell, 2023/06/06
- [PULL 39/42] target/arm: Enable FEAT_LSE2 for -cpu max, Peter Maydell, 2023/06/06
- [PULL 42/42] target/arm: trap DCC access in user mode emulation, Peter Maydell, 2023/06/06
- [PULL 33/42] target/arm: Check alignment in helper_mte_check, Peter Maydell, 2023/06/06
- [PULL 10/42] hw/arm/allwinner-r40: add Clock Control Unit, Peter Maydell, 2023/06/06
- [PULL 11/42] hw: allwinner-r40: Complete uart devices,
Peter Maydell <=
- [PULL 05/42] hw/net/can: Introduce Xilinx Versal CANFD controller, Peter Maydell, 2023/06/06
- [PULL 21/42] target/arm: Add feature test for FEAT_LSE2, Peter Maydell, 2023/06/06
- [PULL 25/42] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G, Peter Maydell, 2023/06/06
- [PULL 26/42] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r, Peter Maydell, 2023/06/06
- [PULL 20/42] target/arm: Add commentary for CPUARMState.exclusive_high, Peter Maydell, 2023/06/06
- [PULL 23/42] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Peter Maydell, 2023/06/06
- [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u, Peter Maydell, 2023/06/06