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[PULL 25/42] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
From: |
Peter Maydell |
Subject: |
[PULL 25/42] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G |
Date: |
Tue, 6 Jun 2023 10:47:57 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This fixes a bug in that these two insns should have been using atomic
16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate-a64.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 3674fc1bc16..35eac7729b0 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -4058,15 +4058,18 @@ static void disas_ldst_tag(DisasContext *s, uint32_t
insn)
if (is_zero) {
TCGv_i64 clean_addr = clean_data_tbi(s, addr);
- TCGv_i64 tcg_zero = tcg_constant_i64(0);
+ TCGv_i64 zero64 = tcg_constant_i64(0);
+ TCGv_i128 zero128 = tcg_temp_new_i128();
int mem_index = get_mem_index(s);
- int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
+ MemOp mop = finalize_memop(s, MO_128 | MO_ALIGN);
- tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index,
- MO_UQ | MO_ALIGN_16);
- for (i = 8; i < n; i += 8) {
- tcg_gen_addi_i64(clean_addr, clean_addr, 8);
- tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ);
+ tcg_gen_concat_i64_i128(zero128, zero64, zero64);
+
+ /* This is 1 or 2 atomic 16-byte operations. */
+ tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop);
+ if (is_pair) {
+ tcg_gen_addi_i64(clean_addr, clean_addr, 16);
+ tcg_gen_qemu_st_i128(zero128, clean_addr, mem_index, mop);
}
}
--
2.34.1
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, (continued)
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, Peter Maydell, 2023/06/06
- [PULL 34/42] target/arm: Add SCTLR.nAA to TBFLAG_A64, Peter Maydell, 2023/06/06
- [PULL 35/42] target/arm: Relax ordered/atomic alignment checks for LSE2, Peter Maydell, 2023/06/06
- [PULL 39/42] target/arm: Enable FEAT_LSE2 for -cpu max, Peter Maydell, 2023/06/06
- [PULL 42/42] target/arm: trap DCC access in user mode emulation, Peter Maydell, 2023/06/06
- [PULL 33/42] target/arm: Check alignment in helper_mte_check, Peter Maydell, 2023/06/06
- [PULL 10/42] hw/arm/allwinner-r40: add Clock Control Unit, Peter Maydell, 2023/06/06
- [PULL 11/42] hw: allwinner-r40: Complete uart devices, Peter Maydell, 2023/06/06
- [PULL 05/42] hw/net/can: Introduce Xilinx Versal CANFD controller, Peter Maydell, 2023/06/06
- [PULL 21/42] target/arm: Add feature test for FEAT_LSE2, Peter Maydell, 2023/06/06
- [PULL 25/42] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G,
Peter Maydell <=
- [PULL 26/42] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r, Peter Maydell, 2023/06/06
- [PULL 20/42] target/arm: Add commentary for CPUARMState.exclusive_high, Peter Maydell, 2023/06/06
- [PULL 23/42] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Peter Maydell, 2023/06/06
- [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u, Peter Maydell, 2023/06/06