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[PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, l
From: |
Peter Maydell |
Subject: |
[PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} |
Date: |
Tue, 6 Jun 2023 10:47:56 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
While we don't require 16-byte atomicity here, using a single larger
operation simplifies the code. Introduce finalize_memop_asimd for this.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/tcg/translate.h | 24 +++++++++++++++++++++++
target/arm/tcg/translate-a64.c | 35 +++++++++++-----------------------
2 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index c1e57a52ca2..3aa486a1ab6 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -609,6 +609,30 @@ static inline MemOp finalize_memop_pair(DisasContext *s,
MemOp opc)
return finalize_memop_atom(s, opc, atom);
}
+/**
+ * finalize_memop_asimd:
+ * @s: DisasContext
+ * @opc: size+sign+align of the memory operation
+ *
+ * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD.
+ */
+static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc)
+{
+ /*
+ * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16,
+ * if IsAligned(8), the first case provides separate atomicity for
+ * the pair of 64-bit accesses. If !IsAligned(8), the middle cases
+ * do not apply, and we're left with the final case of no atomicity.
+ * Thus MO_ATOM_IFALIGN_PAIR.
+ *
+ * For other sizes, normal LSE2 rules apply.
+ */
+ if ((opc & MO_SIZE) == MO_128) {
+ return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR);
+ }
+ return finalize_memop(s, opc);
+}
+
/**
* asimd_imm_const: Expand an encoded SIMD constant value
*
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1fff74c73a0..3674fc1bc16 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -911,26 +911,20 @@ static void do_fp_st(DisasContext *s, int srcidx,
TCGv_i64 tcg_addr, int size)
{
/* This writes the bottom N bits of a 128 bit wide vector to memory */
TCGv_i64 tmplo = tcg_temp_new_i64();
- MemOp mop;
+ MemOp mop = finalize_memop_asimd(s, size);
tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64));
- if (size < 4) {
- mop = finalize_memop(s, size);
+ if (size < MO_128) {
tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
- bool be = s->be_data == MO_BE;
- TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
TCGv_i64 tmphi = tcg_temp_new_i64();
+ TCGv_i128 t16 = tcg_temp_new_i128();
tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx));
+ tcg_gen_concat_i64_i128(t16, tmplo, tmphi);
- mop = s->be_data | MO_UQ;
- tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s),
- mop | (s->align_mem ? MO_ALIGN_16 : 0));
- tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
- tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr,
- get_mem_index(s), mop);
+ tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop);
}
}
@@ -942,24 +936,17 @@ static void do_fp_ld(DisasContext *s, int destidx,
TCGv_i64 tcg_addr, int size)
/* This always zero-extends and writes to a full 128 bit wide vector */
TCGv_i64 tmplo = tcg_temp_new_i64();
TCGv_i64 tmphi = NULL;
- MemOp mop;
+ MemOp mop = finalize_memop_asimd(s, size);
- if (size < 4) {
- mop = finalize_memop(s, size);
+ if (size < MO_128) {
tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
- bool be = s->be_data == MO_BE;
- TCGv_i64 tcg_hiaddr;
+ TCGv_i128 t16 = tcg_temp_new_i128();
+
+ tcg_gen_qemu_ld_i128(t16, tcg_addr, get_mem_index(s), mop);
tmphi = tcg_temp_new_i64();
- tcg_hiaddr = tcg_temp_new_i64();
-
- mop = s->be_data | MO_UQ;
- tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s),
- mop | (s->align_mem ? MO_ALIGN_16 : 0));
- tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
- tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr,
- get_mem_index(s), mop);
+ tcg_gen_extr_i128_i64(tmplo, tmphi, t16);
}
tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
--
2.34.1
- [PULL 12/42] hw: arm: allwinner-r40: Add i2c0 device, (continued)
- [PULL 12/42] hw: arm: allwinner-r40: Add i2c0 device, Peter Maydell, 2023/06/06
- [PULL 15/42] hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support, Peter Maydell, 2023/06/06
- [PULL 14/42] hw/arm/allwinner-r40: add SDRAM controller device, Peter Maydell, 2023/06/06
- [PULL 09/42] hw: arm: Add bananapi M2-Ultra and allwinner-r40 support, Peter Maydell, 2023/06/06
- [PULL 19/42] docs: system: arm: Introduce bananapi_m2u, Peter Maydell, 2023/06/06
- [PULL 28/42] target/arm: Load/store integer pair with one tcg operation, Peter Maydell, 2023/06/06
- [PULL 03/42] hvf: add breakpoint handlers, Peter Maydell, 2023/06/06
- [PULL 08/42] tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller, Peter Maydell, 2023/06/06
- [PULL 13/42] hw/misc: Rename axp209 to axp22x and add support AXP221 PMU, Peter Maydell, 2023/06/06
- [PULL 17/42] hw: arm: allwinner-sramc: Add SRAM Controller support for R40, Peter Maydell, 2023/06/06
- [PULL 24/42] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld},
Peter Maydell <=
- [PULL 32/42] target/arm: Pass single_memop to gen_mte_checkN, Peter Maydell, 2023/06/06
- [PULL 07/42] MAINTAINERS: Include canfd tests under Xilinx CAN, Peter Maydell, 2023/06/06
- [PULL 16/42] hw: arm: allwinner-r40: Add emac and gmac support, Peter Maydell, 2023/06/06
- [PULL 22/42] target/arm: Introduce finalize_memop_{atom,pair}, Peter Maydell, 2023/06/06
- [PULL 31/42] target/arm: Pass memop to gen_mte_check1*, Peter Maydell, 2023/06/06
- [PULL 34/42] target/arm: Add SCTLR.nAA to TBFLAG_A64, Peter Maydell, 2023/06/06
- [PULL 35/42] target/arm: Relax ordered/atomic alignment checks for LSE2, Peter Maydell, 2023/06/06
- [PULL 39/42] target/arm: Enable FEAT_LSE2 for -cpu max, Peter Maydell, 2023/06/06
- [PULL 42/42] target/arm: trap DCC access in user mode emulation, Peter Maydell, 2023/06/06
- [PULL 33/42] target/arm: Check alignment in helper_mte_check, Peter Maydell, 2023/06/06