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[PULL 38/42] tests/tcg/multiarch: Adjust sigbus.c
From: |
Peter Maydell |
Subject: |
[PULL 38/42] tests/tcg/multiarch: Adjust sigbus.c |
Date: |
Tue, 6 Jun 2023 10:48:10 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise
an alignment exception when the load crosses a 16-byte boundary.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230530191438.411344-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/multiarch/sigbus.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/tcg/multiarch/sigbus.c b/tests/tcg/multiarch/sigbus.c
index 8134c5fd568..f47c7390e76 100644
--- a/tests/tcg/multiarch/sigbus.c
+++ b/tests/tcg/multiarch/sigbus.c
@@ -6,8 +6,13 @@
#include <endian.h>
-unsigned long long x = 0x8877665544332211ull;
-void * volatile p = (void *)&x + 1;
+char x[32] __attribute__((aligned(16))) = {
+ 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
+ 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x10,
+ 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
+ 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20,
+};
+void * volatile p = (void *)&x + 15;
void sigbus(int sig, siginfo_t *info, void *uc)
{
@@ -60,9 +65,9 @@ int main()
* We might as well validate the unaligned load worked.
*/
if (BYTE_ORDER == LITTLE_ENDIAN) {
- assert(tmp == 0x55443322);
+ assert(tmp == 0x13121110);
} else {
- assert(tmp == 0x77665544);
+ assert(tmp == 0x10111213);
}
return EXIT_SUCCESS;
}
--
2.34.1
- [PULL 26/42] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r, (continued)
- [PULL 20/42] target/arm: Add commentary for CPUARMState.exclusive_high, Peter Maydell, 2023/06/06
- [PULL 23/42] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Peter Maydell, 2023/06/06
- [PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u, Peter Maydell, 2023/06/06
- [PULL 27/42] target/arm: Sink gen_mte_check1 into load/store_exclusive, Peter Maydell, 2023/06/06
- [PULL 29/42] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}, Peter Maydell, 2023/06/06
- [PULL 37/42] tests/tcg/aarch64: Use stz2g in mte-7.c, Peter Maydell, 2023/06/06
- [PULL 38/42] tests/tcg/multiarch: Adjust sigbus.c,
Peter Maydell <=
- [PULL 36/42] target/arm: Move mte check for store-exclusive, Peter Maydell, 2023/06/06
- [PULL 40/42] target/arm: allow DC CVA[D]P in user mode emulation, Peter Maydell, 2023/06/06
- [PULL 41/42] tests/tcg/aarch64: add DC CVA[D]P tests, Peter Maydell, 2023/06/06
- [PULL 30/42] target/arm: Hoist finalize_memop out of do_fp_{ld, st}, Peter Maydell, 2023/06/06
- Re: [PULL 00/42] target-arm queue, Richard Henderson, 2023/06/06