[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 40/42] target/arm: allow DC CVA[D]P in user mode emulation
From: |
Peter Maydell |
Subject: |
[PULL 40/42] target/arm: allow DC CVA[D]P in user mode emulation |
Date: |
Tue, 6 Jun 2023 10:48:12 +0100 |
From: Zhuojia Shen <chaosdefinition@hotmail.com>
DC CVAP and DC CVADP instructions can be executed in EL0 on Linux,
either directly when SCTLR_EL1.UCI == 1 or emulated by the kernel (see
user_cache_maint_handler() in arch/arm64/kernel/traps.c).
This patch enables execution of the two instructions in user mode
emulation.
Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0b7fd2e7e6c..d4bee43bd01 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7405,7 +7405,6 @@ static const ARMCPRegInfo rndr_reginfo[] = {
.access = PL0_R, .readfn = rndr_readfn },
};
-#ifndef CONFIG_USER_ONLY
static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value)
{
@@ -7420,6 +7419,7 @@ static void dccvap_writefn(CPUARMState *env, const
ARMCPRegInfo *opaque,
/* This won't be crossing page boundaries */
haddr = probe_read(env, vaddr, dline_size, mem_idx, GETPC());
if (haddr) {
+#ifndef CONFIG_USER_ONLY
ram_addr_t offset;
MemoryRegion *mr;
@@ -7430,6 +7430,7 @@ static void dccvap_writefn(CPUARMState *env, const
ARMCPRegInfo *opaque,
if (mr) {
memory_region_writeback(mr, offset, dline_size);
}
+#endif /*CONFIG_USER_ONLY*/
}
}
@@ -7448,7 +7449,6 @@ static const ARMCPRegInfo dcpodp_reg[] = {
.fgt = FGT_DCCVADP,
.accessfn = aa64_cacheop_poc_access, .writefn = dccvap_writefn },
};
-#endif /*CONFIG_USER_ONLY*/
static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo
*ri,
bool isread)
@@ -9092,7 +9092,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (cpu_isar_feature(aa64_tlbios, cpu)) {
define_arm_cp_regs(cpu, tlbios_reginfo);
}
-#ifndef CONFIG_USER_ONLY
/* Data Cache clean instructions up to PoP */
if (cpu_isar_feature(aa64_dcpop, cpu)) {
define_one_arm_cp_reg(cpu, dcpop_reg);
@@ -9101,7 +9100,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, dcpodp_reg);
}
}
-#endif /*CONFIG_USER_ONLY*/
/*
* If full MTE is enabled, add all of the system registers.
--
2.34.1
- Re: [PULL 26/42] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r, (continued)
[PULL 20/42] target/arm: Add commentary for CPUARMState.exclusive_high, Peter Maydell, 2023/06/06
[PULL 23/42] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP, Peter Maydell, 2023/06/06
[PULL 18/42] tests: avocado: boot_linux_console: Add test case for bpim2u, Peter Maydell, 2023/06/06
[PULL 27/42] target/arm: Sink gen_mte_check1 into load/store_exclusive, Peter Maydell, 2023/06/06
[PULL 29/42] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}, Peter Maydell, 2023/06/06
[PULL 37/42] tests/tcg/aarch64: Use stz2g in mte-7.c, Peter Maydell, 2023/06/06
[PULL 38/42] tests/tcg/multiarch: Adjust sigbus.c, Peter Maydell, 2023/06/06
[PULL 36/42] target/arm: Move mte check for store-exclusive, Peter Maydell, 2023/06/06
[PULL 40/42] target/arm: allow DC CVA[D]P in user mode emulation,
Peter Maydell <=
[PULL 41/42] tests/tcg/aarch64: add DC CVA[D]P tests, Peter Maydell, 2023/06/06
[PULL 30/42] target/arm: Hoist finalize_memop out of do_fp_{ld, st}, Peter Maydell, 2023/06/06
Re: [PULL 00/42] target-arm queue, Richard Henderson, 2023/06/06