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[PATCH 08/33] target/mips: Add emulation of Q8ADD instruction
From: |
Siarhei Volkau |
Subject: |
[PATCH 08/33] target/mips: Add emulation of Q8ADD instruction |
Date: |
Thu, 8 Jun 2023 13:41:57 +0300 |
This instruction is used to add/subtract quadruple
8-bit values to another quadruple in parallel.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 77 +++++++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 2c1d7f139e..2eebdfe8ca 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -404,6 +404,7 @@ enum {
OPC_MXU_D16AVGR = 0x03,
OPC_MXU_Q8AVG = 0x04,
OPC_MXU_Q8AVGR = 0x05,
+ OPC_MXU_Q8ADD = 0x07,
};
/*
@@ -1675,6 +1676,79 @@ static void gen_mxu_q8avg(DisasContext *ctx, bool
round45)
}
+/*
+ * MXU instruction category: Arithmetic
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Q8ADD
+ */
+
+/*
+ * Q8ADD XRa, XRb, XRc, ptn2
+ * Add/subtract quadruple of 8-bit packed in XRb
+ * to another one in XRc, put the result in XRa.
+ */
+static void gen_mxu_Q8ADD(DisasContext *ctx)
+{
+ uint32_t aptn2, pad, XRc, XRb, XRa;
+
+ aptn2 = extract32(ctx->opcode, 24, 2);
+ pad = extract32(ctx->opcode, 21, 3);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRa = extract32(ctx->opcode, 6, 4);
+
+ if (unlikely(pad != 0)) {
+ /* opcode padding incorrect -> do nothing */
+ } else if (unlikely(XRa == 0)) {
+ /* destination is zero register -> do nothing */
+ } else if (unlikely((XRb == 0) && (XRc == 0))) {
+ /* both operands zero registers -> just set destination to zero */
+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
+ } else {
+ /* the most general case */
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+ TCGv t4 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t3, XRb);
+ gen_load_mxu_gpr(t4, XRc);
+
+ for (int i = 0; i < 4; i++) {
+ tcg_gen_andi_tl(t0, t3, 0xff);
+ tcg_gen_andi_tl(t1, t4, 0xff);
+
+ if (i < 2) {
+ if (aptn2 & 0x01) {
+ tcg_gen_sub_tl(t0, t0, t1);
+ } else {
+ tcg_gen_add_tl(t0, t0, t1);
+ }
+ } else {
+ if (aptn2 & 0x02) {
+ tcg_gen_sub_tl(t0, t0, t1);
+ } else {
+ tcg_gen_add_tl(t0, t0, t1);
+ }
+ }
+ if (i < 3) {
+ tcg_gen_shri_tl(t3, t3, 8);
+ tcg_gen_shri_tl(t4, t4, 8);
+ }
+ if (i > 0) {
+ tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);
+ } else {
+ tcg_gen_andi_tl(t0, t0, 0xff);
+ tcg_gen_mov_tl(t2, t0);
+ }
+ }
+ gen_store_mxu_gpr(t2, XRa);
+ }
+}
+
+
/*
* MXU instruction category: align
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -2004,6 +2078,9 @@ static void decode_opc_mxu__pool01(DisasContext *ctx)
case OPC_MXU_Q8AVGR:
gen_mxu_q8avg(ctx, true);
break;
+ case OPC_MXU_Q8ADD:
+ gen_mxu_Q8ADD(ctx);
+ break;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
--
2.40.0
- [PATCH 06/33] target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions, (continued)
- [PATCH 06/33] target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions, Siarhei Volkau, 2023/06/08
- [PATCH 11/33] target/mips: Add emulation of MXU D16MACF D16MACE instructions, Siarhei Volkau, 2023/06/08
- [PATCH 02/33] Add support of two XBurst CPUs, Siarhei Volkau, 2023/06/08
- [PATCH 01/33] target/mips: Add emulation of MXU instructions for 32-bit load/store, Siarhei Volkau, 2023/06/08
- [PATCH 07/33] target/mips: Add emulation of MXU S32SLT D16SLT D16AVG[R] Q8AVG[R] insns, Siarhei Volkau, 2023/06/08
- [PATCH 13/33] target/mips: Add emulation of MXU S16MAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 18/33] target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions, Siarhei Volkau, 2023/06/08
- [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions, Siarhei Volkau, 2023/06/08
- [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns, Siarhei Volkau, 2023/06/08
- [PATCH 08/33] target/mips: Add emulation of Q8ADD instruction,
Siarhei Volkau <=
- [PATCH 09/33] target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns, Siarhei Volkau, 2023/06/08
- [PATCH 10/33] target/mips: Add emulation of MXU D16MULF D16MULE instructions, Siarhei Volkau, 2023/06/08
- [PATCH 23/33] target/mips: Add emulation of MXU S32ALN S32LUI insns, Siarhei Volkau, 2023/06/08
- [PATCH 27/33] target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions, Siarhei Volkau, 2023/06/08
- [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions, Siarhei Volkau, 2023/06/08
- [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction, Siarhei Volkau, 2023/06/08
- [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction, Siarhei Volkau, 2023/06/08
- [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction, Siarhei Volkau, 2023/06/08
- [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions, Siarhei Volkau, 2023/06/08